|
| 1 | +# Ideal-Diode Redundant Power Input |
| 2 | + |
| 3 | +This circuit lets either of two DC supplies power one load without allowing |
| 4 | +the active supply to drive current backward into the inactive supply. A 12 V |
| 5 | +primary input normally carries the load. When it fails, an 11.5 V backup takes |
| 6 | +over automatically; when the primary recovers, the circuit hands the load back. |
| 7 | + |
| 8 | +| Property | Value | |
| 9 | +| --- | --- | |
| 10 | +| Requires | `SpiceSharpParser.CustomComponents` ideal diode | |
| 11 | +| Dialect | LTspice-style ideal-diode `.MODEL` | |
| 12 | +| Analysis | TRAN | |
| 13 | +| Difficulty | Intermediate | |
| 14 | +| Main lesson | Supply OR-ing, failover, and reverse-current blocking | |
| 15 | +| Verified with | SpiceSharpParser 3.4.x repository tests | |
| 16 | +| Native LTspice cross-check | Ideal-diode family cross-checked; complete application not yet cross-checked | |
| 17 | + |
| 18 | +## Design Targets |
| 19 | + |
| 20 | +| Target | Value | |
| 21 | +| --- | ---: | |
| 22 | +| Primary supply | 12.0 V | |
| 23 | +| Backup supply | 11.5 V | |
| 24 | +| Load | 12 ohm | |
| 25 | +| Primary source resistance | 100 milliohm | |
| 26 | +| Backup source resistance | 150 milliohm | |
| 27 | +| OR-ing diode on-resistance | 50 milliohm | |
| 28 | +| OR-ing diode forward threshold | 10 mV | |
| 29 | +| Output hold-up capacitance | 100 uF | |
| 30 | +| Primary failure / recovery | 4 ms / 8 ms | |
| 31 | +| Minimum output during failover | Above 11.0 V | |
| 32 | +| Inactive-supply reverse current | Below 1 uA magnitude | |
| 33 | + |
| 34 | +## Schematic |
| 35 | + |
| 36 | + |
| 37 | + |
| 38 | +The node names match |
| 39 | +[ideal-diode-power-or.cir](ideal-diode-power-or.cir). The diode anodes face |
| 40 | +the supplies and their cathodes join at `output`. That orientation permits |
| 41 | +current from either supply to the load while blocking current from the output |
| 42 | +back into a lower or failed supply. |
| 43 | + |
| 44 | +## Runnable Netlist |
| 45 | + |
| 46 | +The essential circuit is: |
| 47 | + |
| 48 | +```spice |
| 49 | +VPRIMARY primary_raw 0 PWL(0 12 4m 12 4.01m 0 8m 0 8.01m 12 12m 12) |
| 50 | +RPRIMARY primary_raw primary_input 100m |
| 51 | +
|
| 52 | +VBACKUP backup_raw 0 11.5 |
| 53 | +RBACKUP backup_raw backup_input 150m |
| 54 | +
|
| 55 | +DPRIMARY primary_input output IDEAL_OR |
| 56 | +DBACKUP backup_input output IDEAL_OR |
| 57 | +.MODEL IDEAL_OR D(Ron=50m Roff=1G Vfwd=10m) |
| 58 | +
|
| 59 | +COUT output 0 100u |
| 60 | +RLOAD output 0 12 |
| 61 | +``` |
| 62 | + |
| 63 | +The complete file adds transient analysis, measurements, saved signals, and a |
| 64 | +plot request. |
| 65 | + |
| 66 | +## How It Works |
| 67 | + |
| 68 | +Here, “OR-ing” means that either supply can power the output. It is not a |
| 69 | +digital OR gate. |
| 70 | + |
| 71 | +### Primary supply available |
| 72 | + |
| 73 | +The 12 V primary produces the higher diode-anode voltage. `DPRIMARY` conducts |
| 74 | +and carries approximately 0.987 A. Its output voltage is high enough to |
| 75 | +reverse-bias `DBACKUP`, so the backup remains connected but supplies |
| 76 | +essentially no current. |
| 77 | + |
| 78 | +### Primary supply fails |
| 79 | + |
| 80 | +At 4 ms, `VPRIMARY` falls to 0 V. `DPRIMARY` turns off and blocks the output |
| 81 | +from discharging into the failed source. `COUT` initially supplies the load, so |
| 82 | +the output voltage begins to fall rather than disappearing immediately. |
| 83 | + |
| 84 | +As soon as the output falls below the backup input by approximately 10 mV, |
| 85 | +`DBACKUP` turns on. The backup then carries approximately 0.942 A and holds the |
| 86 | +output near 11.30 V. |
| 87 | + |
| 88 | +### Primary supply recovers |
| 89 | + |
| 90 | +At 8 ms, the primary returns to 12 V. `DPRIMARY` turns on, raises the output |
| 91 | +back to approximately 11.84 V, and reverse-biases `DBACKUP` again. No explicit |
| 92 | +control signal is needed; the two diode voltages decide which path conducts. |
| 93 | + |
| 94 | +## Design Calculations |
| 95 | + |
| 96 | +When one source is active, its source resistance and diode on-resistance are |
| 97 | +in series with the load. For the primary path: |
| 98 | + |
| 99 | +$$ |
| 100 | +R_{\text{primary path}}=0.10+0.05=0.15\ \Omega |
| 101 | +$$ |
| 102 | + |
| 103 | +Accounting for the 10 mV diode threshold: |
| 104 | + |
| 105 | +$$ |
| 106 | +V_{\text{out,primary}} |
| 107 | +=(12.0-0.01)\frac{12}{12+0.15} |
| 108 | +=11.842\ \text{V} |
| 109 | +$$ |
| 110 | + |
| 111 | +and: |
| 112 | + |
| 113 | +$$ |
| 114 | +I_{\text{primary}} |
| 115 | +=\frac{11.842}{12} |
| 116 | +=0.987\ \text{A} |
| 117 | +$$ |
| 118 | + |
| 119 | +The backup path has 0.15 ohm of source resistance plus 0.05 ohm of diode |
| 120 | +resistance: |
| 121 | + |
| 122 | +$$ |
| 123 | +V_{\text{out,backup}} |
| 124 | +=(11.5-0.01)\frac{12}{12+0.20} |
| 125 | +=11.302\ \text{V} |
| 126 | +$$ |
| 127 | + |
| 128 | +$$ |
| 129 | +I_{\text{backup}} |
| 130 | +=\frac{11.302}{12} |
| 131 | +=0.942\ \text{A} |
| 132 | +$$ |
| 133 | + |
| 134 | +While the backup is active, the failed primary diode sees approximately |
| 135 | +-11.3 V. Its 1 Gohm off resistance predicts: |
| 136 | + |
| 137 | +$$ |
| 138 | +I_{\text{reverse}} |
| 139 | +\approx\frac{-11.3}{1\ \text{G}\Omega} |
| 140 | +=-11.3\ \text{nA} |
| 141 | +$$ |
| 142 | + |
| 143 | +The capacitor stores: |
| 144 | + |
| 145 | +$$ |
| 146 | +E=\frac{1}{2}CV^2 |
| 147 | +\approx\frac{1}{2}(100\ \text{uF})(11.84\ \text{V})^2 |
| 148 | +=7.0\ \text{mJ} |
| 149 | +$$ |
| 150 | + |
| 151 | +In this idealized model, diode switching is immediate, so the failover minimum |
| 152 | +is almost the same as the steady backup voltage. Real controllers and power |
| 153 | +paths introduce additional delay and voltage drop. |
| 154 | + |
| 155 | +## Simulation Setup |
| 156 | + |
| 157 | +The transient analysis runs for 12 ms with a 1 us maximum timestep: |
| 158 | + |
| 159 | +- 0 to 4 ms: primary active, backup blocked; |
| 160 | +- 4 to 8 ms: primary failed, backup active; |
| 161 | +- 8 to 12 ms: primary recovered, backup blocked again. |
| 162 | + |
| 163 | +Measurements avoid the switching instants and average steady portions of each |
| 164 | +state. The failover minimum separately checks the transition from 3.9 to |
| 165 | +4.5 ms. |
| 166 | + |
| 167 | +`.SAVE` and `.PLOT` request the two input nodes, the output bus, and both diode |
| 168 | +currents. |
| 169 | + |
| 170 | + |
| 171 | + |
| 172 | +## Verified Measurements |
| 173 | + |
| 174 | +| Measurement | Acceptance range | Verified result | |
| 175 | +| --- | ---: | ---: | |
| 176 | +| Primary-powered output average | 11.75 to 11.90 V | 11.84198 V | |
| 177 | +| Backup-powered output average | 11.20 to 11.40 V | 11.30164 V | |
| 178 | +| Minimum output during failover | 11.20 to 11.40 V | 11.30164 V | |
| 179 | +| Output after primary recovery | 11.75 to 11.90 V | 11.84198 V | |
| 180 | +| Backup standby current | -10 to +10 nA | -0.342 nA | |
| 181 | +| Backup active current | 0.90 to 0.98 A | 0.94180 A | |
| 182 | +| Current into failed primary | -100 to 0 nA | -11.302 nA | |
| 183 | + |
| 184 | +Negative diode current means current is directed from `output` toward that |
| 185 | +supply. The two nanoampere-scale negative results demonstrate the finite 1 |
| 186 | +Gohm off-state leakage, not an unintended conducting path. |
| 187 | + |
| 188 | +## Experiments |
| 189 | + |
| 190 | +- Lower the backup from 11.5 V to 10 V and observe the larger failover step. |
| 191 | +- Make both supplies 12 V and compare how the source resistances share current. |
| 192 | +- Increase `Ron` to model a higher-loss OR-ing element. |
| 193 | +- Reduce `Roff` to see how off-state leakage can back-power a failed rail. |
| 194 | +- Remove `COUT` and compare the voltage around the 4 ms handoff. |
| 195 | +- Increase `RLOAD` to reduce load current and compare the calculated output |
| 196 | + drop. |
| 197 | +- Add a third diode path to model an auxiliary input. |
| 198 | + |
| 199 | +## Model Boundary |
| 200 | + |
| 201 | +This is a behavioral power-path experiment, not a production ideal-diode |
| 202 | +controller design. The ideal diode is memoryless and omits MOSFET gate-drive |
| 203 | +delay, body-diode conduction, reverse recovery, switching oscillation, current |
| 204 | +limit, thermal behavior, safe operating area, and controller quiescent current. |
| 205 | + |
| 206 | +The supplies use fixed series resistances; they do not model wiring |
| 207 | +inductance, foldback, battery impedance versus state of charge, connector |
| 208 | +bounce, or ground differences. `COUT` has no ESR, ESL, tolerance, or voltage |
| 209 | +rating. |
| 210 | + |
| 211 | +Use the circuit to understand source selection and reverse-current blocking. |
| 212 | +Use vendor controller models, parasitics, tolerances, and fault analysis before |
| 213 | +designing real redundant-power hardware. |
| 214 | + |
| 215 | +## Running and Testing |
| 216 | + |
| 217 | +Enable custom mappings before compilation: |
| 218 | + |
| 219 | +```csharp |
| 220 | +using System; |
| 221 | +using SpiceSharpParser; |
| 222 | +using SpiceSharpParser.CustomComponents; |
| 223 | + |
| 224 | +var options = new SpiceCompileOptions |
| 225 | +{ |
| 226 | + Dialect = SpiceDialect.LTspice, |
| 227 | + ConfigureReader = settings => settings.UseCustomComponents(), |
| 228 | +}; |
| 229 | + |
| 230 | +SpiceCompilationResult result = |
| 231 | + SpiceCompiler.CompileFile("ideal-diode-power-or.cir", options); |
| 232 | + |
| 233 | +if (!result.Success) |
| 234 | +{ |
| 235 | + throw new InvalidOperationException( |
| 236 | + string.Join(Environment.NewLine, result.Diagnostics)); |
| 237 | +} |
| 238 | + |
| 239 | +foreach (var simulation in result.Model.Simulations) |
| 240 | +{ |
| 241 | + simulation.Execute(result.Model.Circuit); |
| 242 | +} |
| 243 | +``` |
| 244 | + |
| 245 | +Run its repository regression test: |
| 246 | + |
| 247 | +```powershell |
| 248 | +dotnet test src/SpiceSharpParser.Tests/SpiceSharpParser.Tests.csproj ` |
| 249 | + --filter 'FullyQualifiedName~CircuitCookbookTests' |
| 250 | +``` |
0 commit comments