Issues

• variable_drivers_group and variable_loads_group reject my loads() and drivers() assignment.

  chipsalliance/UHDM#1102 · Filter by author mlr11 opened on Apr 27, 2025
  1

• VPI: Unable to get driver/load

  chipsalliance/UHDM#1101 · Filter by author heyfey opened on Apr 10, 2025
  5

• Obtaining module handle based on the full name of the instance

  chipsalliance/UHDM#1080 · Filter by author mysoreanoop opened on Jun 28, 2024
  1

• [feature suggestion] Save/restore UHDM in-memory

  chipsalliance/UHDM#902 · Filter by author yurivict opened on Apr 2, 2023
  1

• Create "standalone" examples

  chipsalliance/UHDM#783 · Filter by author alaindargelas opened on Aug 23, 2022
  1

• Consider publishing generated capnp and uhdm_types.h as release artifacts

  chipsalliance/UHDM#498 · Filter by author MikePopoloski opened on Sep 13, 2021
  1

• Support a second parser (other than Surelog)

  enhancement
  chipsalliance/UHDM#319 · Filter by author mithro opened on Jul 24, 2020
  24

• Generate a class hierarchy diagram for generated models

  chipsalliance/UHDM#207 · Filter by author hs-apotell opened on May 7, 2020
  4

• Create SystemVerilog Constraints Model

  chipsalliance/UHDM#185 · Filter by author alaindargelas opened on Apr 22, 2020
  1

• Set up Kokoro CI on this repository

  chipsalliance/UHDM#178 · Filter by author mithro opened on Apr 15, 2020
  1

  

• Run clang-format automatically on everything

  chipsalliance/UHDM#77 · Filter by author mithro opened on Jan 15, 2020
  2

  

• The hand-written classes should have documentation

  documentation
  chipsalliance/UHDM#74 · Filter by author hzeller opened on Jan 15, 2020
  2

• Generate dot file

  enhancement
  chipsalliance/UHDM#73 · Filter by author hzeller opened on Jan 15, 2020
  6

• Add Sphinx document generation and publish to readthedocs.io

  chipsalliance/UHDM#40 · Filter by author mithro opened on Jan 8, 2020
  2