From 30304af6f4321c00757c22c69d77950a845d853a Mon Sep 17 00:00:00 2001 From: Demetrios Chiuratto Agourakis Date: Wed, 23 Sep 2026 23:22:31 +0000 Subject: [PATCH 1/2] insns: fix CCMP immediate template ordering and add CTEST reg, mem symmetry Fixes #316. Fixes #317. 1. In x86/insns.dat, CCMPscc declared the $wdq sbyte# template (opcode 83 /7) before the $bwdq imm# template (opcode 80# /7). For an instruction like: ccmpb {dfv=} [rsp], byte 10 the explicit byte immediate (BITS8) matched sbyteword16 via BYTEEXTMASK promotion in asm/assemble.c. Because [rsp] carried no explicit size, SM1-2 matched both operands to 16 bits, choosing the word template (83 /7) instead of the 8-bit template (80 /7). Placing rm8, imm8 before $wdq sbyte# (matching classic CMP ordering) ensures 8-bit comparisons assemble to 8-bit form. 2. Added symmetric $bwdq CTESTscc spec4,reg#,mem# [wrm: evex... 84# /r] with ND, matching the existing syntactic sugar of legacy TEST reg#,mem#. --- x86/insns.dat | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/x86/insns.dat b/x86/insns.dat index 29a0d810d..84370df26 100644 --- a/x86/insns.dat +++ b/x86/insns.dat @@ -962,10 +962,12 @@ XLAT void [ d7] 8086,ND $bwdq CCMPscc spec4,rm#,reg# [wmr: evex.scc.dfv.l0.m4.o# 38# /r ] APX,SM1-2 $bwdq CCMPscc spec4,reg#,rm# [wrm: evex.scc.dfv.l0.m4.o# 3a# /r ] APX,SM1-2 + CCMPscc spec4,rm8,imm8 [wmi: evex.scc.dfv.l0.m4.o8 80 /7 ib ] APX,SM1-2 $wdq CCMPscc spec4,rm#,sbyte# [wmi: evex.scc.dfv.l0.m4.o# 83 /7 ib,s ] APX,SM1-2 -$bwdq CCMPscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# 80# /7 i# ] APX,SM1-2 +$wdq CCMPscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# 81 /7 i# ] APX,SM1-2 $bwdq CTESTscc spec4,rm#,reg# [wmr: evex.scc.dfv.l0.m4.o# 84# /r ] APX,SM1-2 +$bwdq CTESTscc spec4,reg#,mem# [wrm: evex.scc.dfv.l0.m4.o# 84# /r ] APX,SM1-2,ND $bwdq CTESTscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# f6# /0 i# ] APX,SM1-2 $bwdq CTESTscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# f6# /1 i# ] APX,SM1-2 From 6d9804c4dae8cd359a9efc697002f7a3aa1b711c Mon Sep 17 00:00:00 2001 From: Demetrios Chiuratto Agourakis Date: Thu, 24 Sep 2026 19:17:47 +0000 Subject: [PATCH 2/2] test(apx): add regression fixtures for unsized memory CCMP and CTEST reg, mem syntax --- travis/apx-ccmpscc/apx-ccmpscc.asm | 3 +++ travis/apx-ccmpscc/apx-ccmpscc.bin.t | Bin 6656 -> 6664 bytes travis/apx-ctestscc/apx-ctestscc.asm | 3 +++ travis/apx-ctestscc/apx-ctestscc.bin.t | Bin 3776 -> 3782 bytes 4 files changed, 6 insertions(+) diff --git a/travis/apx-ccmpscc/apx-ccmpscc.asm b/travis/apx-ccmpscc/apx-ccmpscc.asm index 2314b6451..be1852146 100644 --- a/travis/apx-ccmpscc/apx-ccmpscc.asm +++ b/travis/apx-ccmpscc/apx-ccmpscc.asm @@ -1004,3 +1004,6 @@ testcase {0x62, 0xDC, 0x7D, 0x04, 0x83, 0x3A, 0x05}, {ccmpz{dfv=cf,zf,sf,of} wor testcase {0x62, 0xDC, 0x7C, 0x04, 0x83, 0x3A, 0x05}, {ccmpz{dfv=cf,zf,sf,of} dword [r26], byte 0x05} testcase {0x62, 0xDC, 0xFC, 0x04, 0x83, 0x3A, 0x05}, {ccmpz{dfv=cf,zf,sf,of} qword [r26], byte 0x05} + +; Unsized memory operand with explicit byte immediate (issue #316) +testcase {0x62, 0xF4, 0x04, 0x02, 0x80, 0x3C, 0x24, 0x0A}, {ccmpb {dfv=} [rsp], byte 10} diff --git a/travis/apx-ccmpscc/apx-ccmpscc.bin.t b/travis/apx-ccmpscc/apx-ccmpscc.bin.t index b3ae6f52373232c2054a0c433d2ce4e4330e2afc..d66171fb45dbf391ab8ddf3ac94f33654f739a48 100644 GIT binary patch delta 15 WcmZoL=`dL!#gX)dg{i?tg$n>E&jfh@ delta 6 NcmeA$X)swJ1po*z0xJLj diff --git a/travis/apx-ctestscc/apx-ctestscc.asm b/travis/apx-ctestscc/apx-ctestscc.asm index a987578bc..f47dbc3ad 100644 --- a/travis/apx-ctestscc/apx-ctestscc.asm +++ b/travis/apx-ctestscc/apx-ctestscc.asm @@ -555,3 +555,6 @@ testcase {0x62, 0xDC, 0x7C, 0x04, 0xF6, 0x02, 0x05}, {ctestz{dfv=cf,zf,sf,of} by testcase {0x62, 0xDC, 0x7D, 0x04, 0xF7, 0x02, 0x05, 0x00}, {ctestz{dfv=cf,zf,sf,of} word [r26], word 0x05} testcase {0x62, 0xDC, 0x7C, 0x04, 0xF7, 0x02, 0x05, 0x00, 0x00, 0x00}, {ctestz{dfv=cf,zf,sf,of} dword [r26], dword 0x05} testcase {0x62, 0xDC, 0xFC, 0x04, 0xF7, 0x02, 0x05, 0x00, 0x00, 0x00}, {ctestz{dfv=cf,zf,sf,of} qword [r26], dword 0x05} + +; Register-memory operand order symmetry (canonical 84 /r encoding) +testcase {0x62, 0xF4, 0x04, 0x02, 0x84, 0x0A}, {ctestb {dfv=} cl, [rdx]} diff --git a/travis/apx-ctestscc/apx-ctestscc.bin.t b/travis/apx-ctestscc/apx-ctestscc.bin.t index 2a04e65503834eb022d1385374f7dd0016efed00..825da26790b93153346cca513c848055f21a26d0 100644 GIT binary patch delta 14 VcmX>gdrWr20Y0{*FDy(gTmUTq1up;q delta 7 OcmX>mdq8%>0X_f?@dG~q