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[gfx1100] Enable RDNA3 in arch allow-list + Triton GEMM A8W8 tuning config - #4778

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[gfx1100] Enable RDNA3 in arch allow-list + Triton GEMM A8W8 tuning config#4778
okone1995 wants to merge 2 commits into
ROCm:mainfrom
okone1995:gfx1100-aiter-enable

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Summary

Follow-up to #4604 with the working reference implementation discussed there.

vLLM's AITER integration gate (is_aiter_found_and_supported()) covers CDNA3+ and RDNA4, but never gfx1100 (RDNA3) — even though AITER's README lists W7900 / gfx1100 as Experimental, and configs/gemm/ already ships tuned A8W8 configs for gfx1151/1201/1250 but not gfx1100. This PR contributes the aiter-side half of the port (vLLM-side gate change to be submitted separately, tracked in vllm-project/vllm#51136).

Changes

  1. csrc/cpp_itfs/utils.py — add gfx1100 to the allowed_archs list in validate_and_update_archs(). The stale list only covered gfx9x + gfx1151 and rejected GPU_ARCHS=gfx1100 at compile time.
  2. aiter/ops/triton/configs/gemm/gfx1100-GEMM-A8W8.json — new M-band tuning config for the Triton WMMA path (none existed for RDNA3), same M_LEQ_x / M_GEQ_y / any schema as sibling configs:
    • decode (M<=32): BLOCK_SIZE_M=16, N=128, K=128, warps=4, stages=3 -> 0.071 ms/GEMM
    • prefill (M>=64): BLOCK_SIZE_M=64, N=256, warps=8 -> 4.4 ms @ M=2048

Note: AITER's CK-based gemm_a8w8_CK kernels are XDL-only and compile-fail on RDNA3, so gfx1100 routes to the pure-Triton gemm_a8w8 kernel.

Validation (Radeon PRO W7900 48GB, ROCm 7.2.4, vLLM 0.26.0, Aug 3 2026)

Model: Qwen3.6-27B Quark W8A8-INT8, multimodal OCR workload (insurance claim agent, ~4k ctx):

Path Linear kernel Throughput
AITER gated off (default) TritonInt8ScaledMMLinearKernel 12.3 tok/s
AITER gfx1100 (this port) AiterInt8ScaledMMLinearKernel + GDN + causal_conv1d + sampler 11.7 tok/s

Functional parity, not speedup — reported honestly. On this workload the decode bottleneck is 140+ serialized per-layer kernels on RDNA3 WMMA, not a single GEMM. The value here is enabling the native AITER stack (quantized GEMM + GDN decode + conv1d + sampler) on RDNA3 at all; per-shape tuning is left as future work.

Enable with: VLLM_ROCM_USE_AITER=1 GPU_ARCHS=gfx1100; vLLM log confirms Selected AiterInt8ScaledMMLinearKernel.

Only gfx1100 (W7900) is tested; other RDNA3 variants (gfx1101/1102/1103) are expected to work but untested — happy to extend the allow-list if maintainers prefer.

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@okone1995
okone1995 requested a review from a team August 15, 2026 15:21
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🏷️ CI Guide

Runs automatically on every PR:

  • ✅ Pre-checks (submodule verification, code formatting)
  • ✅ Aiter op tests (gfx942 + gfx950)
  • ✅ Triton tests on MI35X (only when aiter/ops/triton/** or related paths are changed)

Extended tests (opt-in via labels):

Label Tests
ci:gfx1250-ffm-triton Run the five-shard gfx1250 FFM Triton test suite
ci:triton-300x Run an additional Triton test job on MI300X in PRs; main branch always runs both MI35X and MI300X
ci:sglang SGLang integration tests: DeepSeek-R1-MXFP4 accuracy, Qwen 3.5 accuracy
ci:atom ATOM benchmark: DeepSeek-R1-0528, GPT-OSS-120B
ci:atom_full ATOM accuracy suite for PR and main models from ATOM models_accuracy.json
ci:vllm vLLM benchmark: GPT-OSS-120B, DeepSeek-R1-0528, Kimi-K2.5
ci:all All standard extended tests (excludes ci:atom_full)

Only add ci:atom_full for FlyDSL or Triton upgrades.
Add labels via the sidebar or gh pr edit 4778 --add-label <label>

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