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Creating a complete SystemVerilog ALU testbench project with Verilator and GTKWave on Ubuntu.

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Name		Name	Last commit message	Last commit date
obj_dir		obj_dir
sim		sim
src		src
Makefile		Makefile
README.md		README.md
dump.vcd		dump.vcd

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Alu-vrification-

Creating a complete SystemVerilog ALU testbench project with Verilator and GTKWave on Ubuntu.

About

Creating a complete SystemVerilog ALU testbench project with Verilator and GTKWave on Ubuntu.

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