Conversation
FPGA-driven NVMe: SQ/CQ/PRP in BRAM, doorbell over PCIe, P2P data path to HBM. RTL under hw/hdl/nvme, driver changes, add example 14 (perf_nvme).
adpp00
changed the title
This branch has not been deployed
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Description
FPGA-driven NVMe stack for the Coyote/SCENIC shell on Alveo U55C. The FPGA builds the NVMe SQ/CQ/PRP structures in BRAM, rings doorbells over PCIe, and supports peer-to-peer DMA from/to device memory(no host round-trip on the data path). Includes multi-vFPGA support with per-region MMU routing, credit arbiter, coyote driver support, and a bandwidth example (
14_perf_nvme).Type of change
Tests & Results
/examples/14_perf_nvmeexample/examples/14_perf_nvmeChecklist