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mdmaas
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vvahidd
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August 26, 2026 03:03
Codecov Report❌ Patch coverage is Additional details and impacted files@@ Coverage Diff @@
## main #242 +/- ##
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+ Coverage 61.62% 62.94% +1.32%
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Files 105 106 +1
Lines 15304 16002 +698
Branches 3029 3144 +115
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+ Hits 9431 10073 +642
- Misses 4882 4903 +21
- Partials 991 1026 +35 ☔ View full report in Codecov by Harness. 🚀 New features to boost your workflow:
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Consolidate stack/junction.py + stack/doping.py into stack/pn_junction.py and the three pn-junction test files into tests/common/test_pn_junction.py. Add the 1D free-carrier plasma-dispersion model (carrier_profile_1d, epsilon_eff_relative, optical_params, junction_epsilon_profile) with SI-correct units, plus make_segmented_junction_profile (8+8 uniform p_1..n_8 strips sampling the Sze permittivity at strip centres). The palace_2d_twmzm optical run now uses the segmented rib with per-strip free-carrier materials (Re(eps)->Permittivity, Im(eps)->Conductivity); build_optical_cross_section() accepts per-region device_materials and extra_materials to support it.
Add postprocessing-only lumped/CPW ports to BoundaryModeSim. These do not load the 2D eigenproblem; Palace evaluates the port voltage paths after the mode is found and writes mode-V.csv (complex integrated voltage) and mode-Z.csv (characteristic impedance Z_PV/L_PV/C_PV, plus Z_VI/L_VI/C_VI when a CurrentPath is given). - PortConfig/CPWPortConfig gain voltage_path(s)/current_path/nsamples plus center/orientation/width/order; add_port/add_cpw_port thread them through. - Derive cross-section voltage paths from port + stack geometry, or accept explicit 2D/3D paths; emit Boundaries.Postprocessing for boundarymode. - Allow lumped/CPW ports in BoundaryModeSim (wave ports still rejected). - Parse mode-Z.csv/mode-V.csv in PalaceTextResults via characteristic_impedance() and mode_voltage(). - TW-MZM notebook: add gdsfactory rf_in (CPW/GSG on metal1) and junction (lumped, WG at the PN junction) ports, and report the RF line impedance and junction V_bias.
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Summary
Implements a PN-junction depletion model for the 2D TW-MZM workflow, replacing the hand-picked junction capacitance with textbook physics. Builds on #233 (contains its commits; this PR shrinks to the feature commit once #233 merges).
Formulas (Sze & Ng, Physics of Semiconductor Devices, 3rd ed., Wiley, ch. 2)
Built-in voltage:
Abrupt-junction depletion width under reverse bias$V_R$ :
Asymmetric split of the depletion into the two sides:
Linearly graded junction (grade constant$a = |dN/dx|$ ):
Depletion capacitance:
Doping concentrations use the industry-standard$\mathrm{cm^{-3}}$ ; lengths in µm.
User API
Two representation modes, auto-selected from$W$ vs the flanking doped sections — high-res when $W \ge \tfrac{1}{5}\min(\text{P flank},\text{N flank})$ , capacitance otherwise (manual override via
mode=):The profile builder returns the doped regions, the P/N regions, and the junction metadata (widths/capacitance/chosen mode):
Demo
The 2d_twmzm notebook now illustrates this: the default junction ($N_A=N_D=10^{18},\mathrm{cm^{-3}}$ , $V_R=0$ , with $T$ and $n_i$ exposed as user parameters) gives $W \approx 50$ nm and auto-selects high-res mode — the depletion strip is drawn on the actual mesh. A doping sweep in the demo shows $W$ crossing back below the threshold into capacitance mode at heavier doping.
Also fixed
build_doped_cross_section()never registered the merged doping/rib materials onstack.materials, so doped domains silently resolved to eps=1.0 without conductivity in generated Palace configs (visible in prior demo artifacts). Now registered, with regression test.Tests
41 new tests: physics values/limits/scalings and error paths, profile geometry/materials/auto-mode boundary cases, and end-to-end Palace checks (Impedance$C_s$ value in capacitance mode; junction dielectric domain group with $\varepsilon = 11.9$ /no conductivity in high-res mode).