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tinyMIPS

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an uncompleted tiny MIPS32 soft core based on Altera Cyclone-IV EP4CE10F17C8

fpga-programming softcore verilog-project

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Name		Name	Last commit message	Last commit date
LLbit_reg.v		LLbit_reg.v
README.md		README.md
async_fifo.v		async_fifo.v
cp0_reg.v		cp0_reg.v
ctrl.v		ctrl.v
ex.v		ex.v
ex_mem.v		ex_mem.v
flash_top.v		flash_top.v
id.v		id.v
id_ex.v		id_ex.v
if_id.v		if_id.v
inst_rom.v		inst_rom.v
macro.v		macro.v
mem.v		mem.v
mem_wb.v		mem_wb.v
openmips.v		openmips.v
pc_reg.v		pc_reg.v
raminfr.v		raminfr.v
regs.v		regs.v
sdrc_bank_ctl.v		sdrc_bank_ctl.v
sdrc_bank_fsm.v		sdrc_bank_fsm.v
sdrc_bs_convert.v		sdrc_bs_convert.v
sdrc_core.v		sdrc_core.v
sdrc_define.v		sdrc_define.v
sdrc_req_gen.v		sdrc_req_gen.v
sdrc_top.v		sdrc_top.v
sdrc_top.v.bak		sdrc_top.v.bak
sdrc_xfr_ctl.v		sdrc_xfr_ctl.v
sync_fifo.v		sync_fifo.v
timescale.v		timescale.v
tinyMIPS.qpf		tinyMIPS.qpf
tinyMIPS.v		tinyMIPS.v
uart_debug_if.v		uart_debug_if.v
uart_defines.v		uart_defines.v
uart_receiver.v		uart_receiver.v
uart_regs.v		uart_regs.v
uart_rfifo.v		uart_rfifo.v
uart_sync_flops.v		uart_sync_flops.v
uart_tfifo.v		uart_tfifo.v
uart_top.v		uart_top.v
uart_transmitter.v		uart_transmitter.v
uart_wb.v		uart_wb.v
wb2sdrc.v		wb2sdrc.v
wb_conmax_rf.v		wb_conmax_rf.v
wishbone_bus_if.v		wishbone_bus_if.v

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tinyMIPS

a nearly completed tiny MIPS32 soft core based on Altera Cyclone-IV EP4CE10F17C8.

i am going to add more features, like a couple of floating point multiplication acceleration coprocessors.

About

an uncompleted tiny MIPS32 soft core based on Altera Cyclone-IV EP4CE10F17C8

fpga-programming softcore verilog-project

1 star

1 watching

Report repository

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