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tdx: normalize TDX max_phys_bits handling - #14

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zhoul1/dev/tdx_dev_1
Aug 25, 2026
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tdx: normalize TDX max_phys_bits handling#14
guzongmin merged 1 commit into
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zhoul1/dev/tdx_dev_1

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Normalize TDX max_phys_bits in VM config validation to supported GPA widths (48/52), make x86 CPUID phys-bits reporting follow the validated config value.

@liangzhou121
liangzhou121 requested a lite review from Copilot August 25, 2026 08:35
@guzongmin
guzongmin merged commit a23e88f into main Aug 25, 2026
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Pull request overview

This PR normalizes TDX guest physical address width selection during VM configuration validation (to the supported 48/52-bit GPA widths) and adjusts x86 CPUID reporting to follow the validated physical-bits configuration, while updating TDX documentation examples accordingly.

Changes:

  • Normalize --cpus max_phys_bits for TDX to either 48 (4-level EPT) or 52 (5-level EPT) during VmConfig::validate().
  • Update x86 CPUID leaf 0x8000_0008 handling to align physical-bits reporting with the config.
  • Remove max_phys_bits=52 from TDX documentation command examples and add a unit test for the new normalization behavior.

Reviewed changes

Copilot reviewed 3 out of 3 changed files in this pull request and generated 2 comments.

File Description
vmm/src/config.rs Normalizes TDX max_phys_bits during validation and adds a unit test for 48/52 behavior.
arch/src/x86_64/mod.rs Changes CPUID leaf 0x8000_0008 bitfield population to reflect configured phys-bits.
docs/intel_tdx.md Updates TDX run examples to no longer require explicitly setting max_phys_bits.

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Comment thread arch/src/x86_64/mod.rs
Comment on lines +716 to +718
entry.eax = (entry.eax & 0xff00_ff00)
| (config.phys_bits as u32 & 0xff)
| ((config.phys_bits as u32 & 0xff) << 16);
Comment thread vmm/src/config.rs
Comment on lines +4926 to +4928
tdx_config.cpus.max_phys_bits = 52;
tdx_config.validate().unwrap();
assert_eq!(tdx_config.cpus.max_phys_bits, 52);
Normalize TDX max_phys_bits in VM config validation to supported GPA widths (48/52), make x86 CPUID phys-bits reporting follow the validated config value.

Signed-off-by: Liang, Zhou <liang1.zhou@intel.com>
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3 participants