tdx: normalize TDX max_phys_bits handling - #14
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Pull request overview
This PR normalizes TDX guest physical address width selection during VM configuration validation (to the supported 48/52-bit GPA widths) and adjusts x86 CPUID reporting to follow the validated physical-bits configuration, while updating TDX documentation examples accordingly.
Changes:
- Normalize
--cpus max_phys_bitsfor TDX to either 48 (4-level EPT) or 52 (5-level EPT) duringVmConfig::validate(). - Update x86 CPUID leaf
0x8000_0008handling to align physical-bits reporting with the config. - Remove
max_phys_bits=52from TDX documentation command examples and add a unit test for the new normalization behavior.
Reviewed changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated 2 comments.
| File | Description |
|---|---|
vmm/src/config.rs |
Normalizes TDX max_phys_bits during validation and adds a unit test for 48/52 behavior. |
arch/src/x86_64/mod.rs |
Changes CPUID leaf 0x8000_0008 bitfield population to reflect configured phys-bits. |
docs/intel_tdx.md |
Updates TDX run examples to no longer require explicitly setting max_phys_bits. |
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| entry.eax = (entry.eax & 0xff00_ff00) | ||
| | (config.phys_bits as u32 & 0xff) | ||
| | ((config.phys_bits as u32 & 0xff) << 16); |
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| tdx_config.cpus.max_phys_bits = 52; | ||
| tdx_config.validate().unwrap(); | ||
| assert_eq!(tdx_config.cpus.max_phys_bits, 52); |
Normalize TDX max_phys_bits in VM config validation to supported GPA widths (48/52), make x86 CPUID phys-bits reporting follow the validated config value. Signed-off-by: Liang, Zhou <liang1.zhou@intel.com>
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Normalize TDX max_phys_bits in VM config validation to supported GPA widths (48/52), make x86 CPUID phys-bits reporting follow the validated config value.