tdx: mask CPUID.0xD using TDX supported_xfam

[liangzhou121]

No description provided.

[Copilot]

🟡 Changes recommended

The new TDX CPUID.0xD masking should also zero masked-out per-state subleafs (and align advertised XFAM with the CET-masked XFAM used during TDX init) to avoid exposing inconsistent/unsupported XSAVE component data to the guest.

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Pull request overview

This PR updates x86 CPUID generation to support TDX by masking CPUID leaf 0xD (XSAVE state) based on TDX supported_xfam, wiring a VM handle into the CPUID generation path when TDX is enabled.

Changes:

• Extend arch::generate_common_cpuid() (under feature = "tdx") to optionally take a VM handle and apply TDX-specific CPUID.0xD masking.
• Update VMM call sites to pass a VM handle when generating CPUID for TDX-capable builds, and pass None in snapshot/migration paths that explicitly disallow TDX.
• Add TDX-specific CPUID configuration helper to apply the supported_xfam mask.

File summaries

File	Description
arch/src/x86_64/mod.rs	Adds TDX-aware CPUID generation by masking CPUID.0xD using TDX capabilities fetched from the VM.
vmm/src/cpu.rs	Passes TDX mode (including VM handle) into common CPUID generation when TDX is enabled.
vmm/src/lib.rs	Updates migration CPUID generation call sites for TDX-enabled builds (passing None since TDX migration is rejected).
vmm/src/vm.rs	Updates snapshot CPUID generation call site for TDX-enabled builds (passing None since TDX snapshot is rejected).

Review details

• Files reviewed: 4/4 changed files
• Comments generated: 2
• Review effort level: Lite

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[guzongmin]

LGTM

[guzongmin]

// Bit 8: PT (Processor Trace)
// Bit 11: CET_U (User Shadow Stack)
// Bit 12: CET_S (Supervisor Shadow Stack)
// Bit 13: HDC
// Bit 14: UINTR (User Interrupts)
// Bit 15: LBR (Last Branch Record)
const XSS_PT_BIT: u64 = 8;
const XSS_CET_U_BIT: u64 = 11;
const XSS_CET_S_BIT: u64 = 12;
const XSS_HDC_BIT: u64 = 13;
const XSS_UINTR_BIT: u64 = 14;
const XSS_LBR_BIT: u64 = 15;

let xss_mask: u64 = (1 << XSS_PT_BIT)
| (1 << XSS_CET_U_BIT)
| (1 << XSS_CET_S_BIT)
| (1 << XSS_HDC_BIT)
| (1 << XSS_UINTR_BIT)
| (1 << XSS_LBR_BIT);

better than let xss_mask: u64 = !xcr0_mask;