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Pull requests: nanavati/bsc

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Pull requests list

Add negative literal patterns
#15 opened Aug 16, 2026 by nanavati Owner Loading…
Support Real literal patterns in BSV
#13 opened Aug 16, 2026 by nanavati Owner Loading…
IExpand: replace the SYB traversal in removeInlinedPositions
#9 opened Jul 17, 2026 by nanavati Owner Loading…
Fix two quadratic blowups in foreign-block Verilog generation
#8 opened Jul 17, 2026 by nanavati Owner Loading…
Add an -elab-only flag: stop compilation at the .ba
#7 opened Jul 15, 2026 by nanavati Owner Loading…
Verilator as a first-class simulator: integration branch
#3 opened Jul 4, 2026 by nanavati Owner Loading…
Regenerate missing or stale Verilog when linking
#2 opened Jul 2, 2026 by nanavati Owner Loading…
Support -c codegen mode for Bluesim and Verilog
#1 opened Jul 2, 2026 by nanavati Owner Loading…
ProTip! Updated in the last three days: updated:>2026-08-17.