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3 changes: 3 additions & 0 deletions travis/apx-ccmpscc/apx-ccmpscc.asm
Original file line number Diff line number Diff line change
Expand Up @@ -1004,3 +1004,6 @@ testcase {0x62, 0xDC, 0x7D, 0x04, 0x83, 0x3A, 0x05}, {ccmpz{dfv=cf,zf,sf,of} wor
testcase {0x62, 0xDC, 0x7C, 0x04, 0x83, 0x3A, 0x05}, {ccmpz{dfv=cf,zf,sf,of} dword [r26], byte 0x05}
testcase {0x62, 0xDC, 0xFC, 0x04, 0x83, 0x3A, 0x05}, {ccmpz{dfv=cf,zf,sf,of} qword [r26], byte 0x05}


; Unsized memory operand with explicit byte immediate (issue #316)
testcase {0x62, 0xF4, 0x04, 0x02, 0x80, 0x3C, 0x24, 0x0A}, {ccmpb {dfv=} [rsp], byte 10}
Binary file modified travis/apx-ccmpscc/apx-ccmpscc.bin.t
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3 changes: 3 additions & 0 deletions travis/apx-ctestscc/apx-ctestscc.asm
Original file line number Diff line number Diff line change
Expand Up @@ -555,3 +555,6 @@ testcase {0x62, 0xDC, 0x7C, 0x04, 0xF6, 0x02, 0x05}, {ctestz{dfv=cf,zf,sf,of} by
testcase {0x62, 0xDC, 0x7D, 0x04, 0xF7, 0x02, 0x05, 0x00}, {ctestz{dfv=cf,zf,sf,of} word [r26], word 0x05}
testcase {0x62, 0xDC, 0x7C, 0x04, 0xF7, 0x02, 0x05, 0x00, 0x00, 0x00}, {ctestz{dfv=cf,zf,sf,of} dword [r26], dword 0x05}
testcase {0x62, 0xDC, 0xFC, 0x04, 0xF7, 0x02, 0x05, 0x00, 0x00, 0x00}, {ctestz{dfv=cf,zf,sf,of} qword [r26], dword 0x05}

; Register-memory operand order symmetry (canonical 84 /r encoding)
testcase {0x62, 0xF4, 0x04, 0x02, 0x84, 0x0A}, {ctestb {dfv=} cl, [rdx]}
Binary file modified travis/apx-ctestscc/apx-ctestscc.bin.t
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4 changes: 3 additions & 1 deletion x86/insns.dat
Original file line number Diff line number Diff line change
Expand Up @@ -962,10 +962,12 @@ XLAT void [ d7] 8086,ND

$bwdq CCMPscc spec4,rm#,reg# [wmr: evex.scc.dfv.l0.m4.o# 38# /r ] APX,SM1-2
$bwdq CCMPscc spec4,reg#,rm# [wrm: evex.scc.dfv.l0.m4.o# 3a# /r ] APX,SM1-2
CCMPscc spec4,rm8,imm8 [wmi: evex.scc.dfv.l0.m4.o8 80 /7 ib ] APX,SM1-2
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$wdq CCMPscc spec4,rm#,sbyte# [wmi: evex.scc.dfv.l0.m4.o# 83 /7 ib,s ] APX,SM1-2
$bwdq CCMPscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# 80# /7 i# ] APX,SM1-2
$wdq CCMPscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# 81 /7 i# ] APX,SM1-2

$bwdq CTESTscc spec4,rm#,reg# [wmr: evex.scc.dfv.l0.m4.o# 84# /r ] APX,SM1-2
$bwdq CTESTscc spec4,reg#,mem# [wrm: evex.scc.dfv.l0.m4.o# 84# /r ] APX,SM1-2,ND
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$bwdq CTESTscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# f6# /0 i# ] APX,SM1-2
$bwdq CTESTscc spec4,rm#,imm# [wmi: evex.scc.dfv.l0.m4.o# f6# /1 i# ] APX,SM1-2

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