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UCT/IB/RC/VERBS: Support QPs without SRQ #11933

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2ca3b5e
AUTHORS: add Guangguan Wang
GuangguanWang Sep 10, 2026
0f4f496
UCT/IB/RC: Add RC interface initialization attributes
GuangguanWang Sep 9, 2026
abaaa2d
UCT/IB/RC: Add receive queue length to QP creation
GuangguanWang Sep 9, 2026
ed613fc
UCT/IB: Add uct_ib_device_has_srq()
GuangguanWang Sep 9, 2026
dbedcbf
UCT/IB/RC: Remove an endpoint from ep_list in uct_rc_ep_t cleanup
GuangguanWang Sep 9, 2026
6ca8320
UCT/IB/RC/VERBS: Release the descriptor of a failed receive completion
GuangguanWang Sep 10, 2026
ac4b1fe
UCT/IB/RC/VERBS: Support QPs without SRQ
GuangguanWang Sep 9, 2026
ac194c1
GTEST/UCT/IB: Skip LAST_WQE tests when the QPs have no SRQ
GuangguanWang Sep 9, 2026
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1 change: 1 addition & 0 deletions AUTHORS
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@ Gilbert Lee <gilbert.lee@amd.com>
Gilles Gouaillardet <gilles.gouaillardet@gmail.com>
Gonzalo Brito Gadeschi <gonzalob@nvidia.com>
Graham Lopez <lopezmg@ornl.gov>
Guangguan Wang <guangguan.wang@linux.alibaba.com>
Guy Ealey Morag <gealeymorag@nvidia.com>
Guy Shattah <sguy@mellanox.com>
Hannes Hansen <mail@hannesh.de>
Expand Down
2 changes: 1 addition & 1 deletion src/uct/ib/base/ib_device.c
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Expand Up @@ -801,7 +801,7 @@ uct_ib_device_port_check(uct_ib_device_t *dev, uint8_t port_num, unsigned flags)
}

if (flags & UCT_IB_DEVICE_FLAG_SRQ) {
if (IBV_DEV_ATTR(dev, max_srq) == 0) {
if (!uct_ib_device_has_srq(dev)) {
ucs_trace("%s:%d does not support SRQ", uct_ib_device_name(dev),
port_num);
return UCS_ERR_UNSUPPORTED;
Expand Down
5 changes: 5 additions & 0 deletions src/uct/ib/base/ib_device.h
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Expand Up @@ -440,6 +440,11 @@ static inline int uct_ib_device_has_pci_atomics(uct_ib_device_t *dev)
(sizeof(uint32_t) | sizeof(uint64_t)));
}

static inline int uct_ib_device_has_srq(uct_ib_device_t *dev)
{
return IBV_DEV_ATTR(dev, max_srq) != 0;
}

const char *uct_ib_roce_version_str(uct_ib_roce_version_t roce_ver);

const char *uct_ib_gid_str(const union ibv_gid *gid, char *str, size_t max_size);
Expand Down
22 changes: 11 additions & 11 deletions src/uct/ib/mlx5/dc/dc_mlx5.c
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Expand Up @@ -1667,7 +1667,7 @@ static UCS_CLASS_INIT_FUNC(uct_dc_mlx5_iface_t, uct_md_h tl_md, uct_worker_h wor
uct_dc_mlx5_iface_config_t);
uct_ib_mlx5_md_t *md = ucs_derived_of(tl_md,
uct_ib_mlx5_md_t);
uct_ib_iface_init_attr_t init_attr = {};
uct_rc_iface_init_attr_t init_attr = {};
unsigned tx_queue_len = config->super.super.tx.queue_len;
size_t sq_length;
ucs_status_t status;
Expand Down Expand Up @@ -1697,28 +1697,28 @@ static UCS_CLASS_INIT_FUNC(uct_dc_mlx5_iface_t, uct_md_h tl_md, uct_worker_h wor
UCT_DC_MLX5_HW_DCI_INDEX :
-1;

init_attr.qp_type = UCT_IB_QPT_DCI;
init_attr.flags = UCT_IB_TX_OPS_PER_PATH;
init_attr.fc_req_size = sizeof(uct_dc_fc_request_t);
init_attr.max_rd_atomic = md->max_rd_atomic_dc;
init_attr.tx_moderation = 0; /* disable tx moderation for dcs */
init_attr.dev_name = params->mode.device.dev_name;
init_attr.super.qp_type = UCT_IB_QPT_DCI;
init_attr.super.flags = UCT_IB_TX_OPS_PER_PATH;
init_attr.super.fc_req_size = sizeof(uct_dc_fc_request_t);
init_attr.super.max_rd_atomic = md->max_rd_atomic_dc;
init_attr.super.tx_moderation = 0; /* disable tx moderation for dcs */
init_attr.super.dev_name = params->mode.device.dev_name;

if (md->flags & UCT_IB_MLX5_MD_FLAG_DC_TM) {
init_attr.flags |= UCT_IB_TM_SUPPORTED;
init_attr.super.flags |= UCT_IB_TM_SUPPORTED;
}

if ((md->dp_ordering_cap_devx.dc == UCT_IB_MLX5_DP_ORDERING_OOO_ALL) ||
md->ddp_support_dv.dc) {
init_attr.flags |= UCT_IB_DDP_SUPPORTED;
init_attr.super.flags |= UCT_IB_DDP_SUPPORTED;
}

status = uct_dc_mlx5_calc_sq_length(md, tx_queue_len, &sq_length);
if (status != UCS_OK) {
return status;
}

init_attr.cq_len[UCT_IB_DIR_TX] = sq_length * self->tx.ndci;
init_attr.super.cq_len[UCT_IB_DIR_TX] = sq_length * self->tx.ndci;

status = uct_rc_mlx5_dp_ordering_ooo_init(md, &self->super,
md->dp_ordering_cap_devx.dc,
Expand All @@ -1734,7 +1734,7 @@ static UCS_CLASS_INIT_FUNC(uct_dc_mlx5_iface_t, uct_md_h tl_md, uct_worker_h wor
tl_md, worker, params, &config->super,
&config->rc_mlx5_common, &init_attr);

tx_cq_size = uct_ib_cq_size(&self->super.super.super, &init_attr,
tx_cq_size = uct_ib_cq_size(&self->super.super.super, &init_attr.super,
UCT_IB_DIR_TX);

/* driver will round up num cqes to pow of 2 if needed */
Expand Down
17 changes: 9 additions & 8 deletions src/uct/ib/mlx5/gdaki/gdaki.c
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Expand Up @@ -483,7 +483,7 @@ uct_rc_gdaki_init_channel_chunk(uct_rc_gdaki_iface_t *iface,
uct_ib_mlx5_cq_calc_sizes(&iface->super.super.super, UCT_IB_DIR_TX,
&init_attr, 0, &cq_attr);
uct_rc_iface_fill_attr(&iface->super.super, &qp_attr.super,
iface->super.super.config.tx_qp_len, NULL);
iface->super.super.config.tx_qp_len, 0, NULL);

cq_attr.flags |= UCT_IB_MLX5_CQ_IGNORE_OVERRUN;
qp_attr.mmio_mode = UCT_IB_MLX5_MMIO_MODE_DB;
Expand Down Expand Up @@ -647,7 +647,7 @@ uct_rc_gdaki_iface_init_channel_pool(uct_rc_gdaki_iface_t *iface,
}

uct_rc_iface_fill_attr(&iface->super.super, &qp_attr.super,
iface->super.super.config.tx_qp_len, NULL);
iface->super.super.config.tx_qp_len, 0, NULL);
uct_ib_mlx5_wq_calc_sizes(&qp_attr);

priv = ucs_mpool_priv(&iface->channel_pool);
Expand Down Expand Up @@ -711,7 +711,7 @@ uct_rc_gdaki_ep_init_channels_direct(uct_rc_gdaki_iface_t *iface,
ucs_status_t status;

uct_rc_iface_fill_attr(&iface->super.super, &qp_attr.super,
iface->super.super.config.tx_qp_len, NULL);
iface->super.super.config.tx_qp_len, 0, NULL);
uct_ib_mlx5_wq_calc_sizes(&qp_attr);
uct_rc_gdaki_calc_dev_ep_layout(iface->num_channels, qp_attr.len,
&dev_ep_size, &pgsz_bitmap);
Expand Down Expand Up @@ -1153,7 +1153,7 @@ static UCS_CLASS_INIT_FUNC(uct_rc_gdaki_iface_t, uct_md_h tl_md,
uct_rc_gdaki_iface_config_t *config =
ucs_derived_of(tl_config, uct_rc_gdaki_iface_config_t);
uct_ib_mlx5_md_t *md = ucs_derived_of(tl_md, uct_ib_mlx5_md_t);
uct_ib_iface_init_attr_t init_attr = {};
uct_rc_iface_init_attr_t init_attr = {};
uct_md_mem_reg_params_t reg_params = {};
UCS_STRING_BUFFER_ONSTACK(strb, 64);
char *gpu_name, *ib_name;
Expand Down Expand Up @@ -1183,10 +1183,11 @@ static UCS_CLASS_INIT_FUNC(uct_rc_gdaki_iface_t, uct_md_h tl_md,
gpu_name = ucs_string_buffer_next_token(&strb, NULL, "-");
ib_name = ucs_string_buffer_next_token(&strb, gpu_name, "-");

init_attr.seg_size = config->super.super.seg_size;
init_attr.qp_type = IBV_QPT_RC;
init_attr.dev_name = ib_name;
init_attr.max_rd_atomic = IBV_DEV_ATTR(&md->super.dev, max_qp_rd_atom);
init_attr.super.seg_size = config->super.super.seg_size;
init_attr.super.qp_type = IBV_QPT_RC;
init_attr.super.dev_name = ib_name;
init_attr.super.max_rd_atomic = IBV_DEV_ATTR(&md->super.dev,
max_qp_rd_atom);

UCS_CLASS_CALL_SUPER_INIT(uct_rc_mlx5_iface_common_t,
&uct_rc_gdaki_iface_tl_ops,
Expand Down
21 changes: 10 additions & 11 deletions src/uct/ib/mlx5/gga/gga_mlx5.c
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Expand Up @@ -470,7 +470,6 @@ static UCS_CLASS_CLEANUP_FUNC(uct_gga_mlx5_ep_t)
uct_rc_iface_remove_qp(&iface->super, self->super.tx.wq.super.qp_num);
uct_ib_mlx5_destroy_qp(md, &self->super.tx.wq.super);
uct_ib_mlx5_qp_mmio_cleanup(&self->super.tx.wq.super, self->super.tx.wq.reg);
ucs_list_del(&self->super.super.list);
uct_rc_iface_add_cq_credits(&iface->super, outstanding - wqe_count);
}

Expand Down Expand Up @@ -773,19 +772,19 @@ static UCS_CLASS_INIT_FUNC(uct_gga_mlx5_iface_t,
uct_gga_mlx5_iface_config_t *config =
ucs_derived_of(tl_config, uct_gga_mlx5_iface_config_t);
uct_ib_mlx5_md_t *md = ucs_derived_of(tl_md, uct_ib_mlx5_md_t);
uct_ib_iface_init_attr_t init_attr = {};
uct_rc_iface_init_attr_t init_attr = {};
ucs_status_t status;
uct_ib_mlx5_dp_ordering_t dp_ordering;

init_attr.xport_hdr_len = UCT_IB_RETH_LEN;
init_attr.qp_type = IBV_QPT_RC;
init_attr.cq_len[UCT_IB_DIR_TX] = config->super.tx_cq_len;
init_attr.max_rd_atomic = IBV_DEV_ATTR(&md->super.dev,
max_qp_rd_atom);
init_attr.tx_moderation = config->super.tx_cq_moderation;
init_attr.dev_name = params->mode.device.dev_name;
dp_ordering = ucs_min(md->dp_ordering_cap_devx.rc,
UCT_IB_MLX5_DP_ORDERING_OOO_RW);
init_attr.super.xport_hdr_len = UCT_IB_RETH_LEN;
init_attr.super.qp_type = IBV_QPT_RC;
init_attr.super.cq_len[UCT_IB_DIR_TX] = config->super.tx_cq_len;
init_attr.super.max_rd_atomic = IBV_DEV_ATTR(&md->super.dev,
max_qp_rd_atom);
init_attr.super.tx_moderation = config->super.tx_cq_moderation;
init_attr.super.dev_name = params->mode.device.dev_name;
dp_ordering = ucs_min(md->dp_ordering_cap_devx.rc,
UCT_IB_MLX5_DP_ORDERING_OOO_RW);

status = uct_rc_mlx5_dp_ordering_ooo_init(md, &self->super, dp_ordering, 0,
&config->rc_mlx5_common, "gga");
Expand Down
5 changes: 3 additions & 2 deletions src/uct/ib/mlx5/rc/rc_mlx5_common.c
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Expand Up @@ -528,12 +528,13 @@ void uct_rc_mlx5_iface_fill_attr(uct_rc_mlx5_iface_common_t *iface,
{
switch (srq->type) {
case UCT_IB_MLX5_OBJ_TYPE_VERBS:
uct_rc_iface_fill_attr(&iface->super, &qp_attr->super, max_send_wr,
uct_rc_iface_fill_attr(&iface->super, &qp_attr->super, max_send_wr, 0,
srq->verbs.srq);
break;
case UCT_IB_MLX5_OBJ_TYPE_DEVX:
case UCT_IB_MLX5_OBJ_TYPE_NULL:
uct_rc_iface_fill_attr(&iface->super, &qp_attr->super, max_send_wr, NULL);
uct_rc_iface_fill_attr(&iface->super, &qp_attr->super, max_send_wr, 0,
NULL);
break;
case UCT_IB_MLX5_OBJ_TYPE_LAST:
break;
Expand Down
2 changes: 1 addition & 1 deletion src/uct/ib/mlx5/rc/rc_mlx5_common.h
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Expand Up @@ -441,7 +441,7 @@ UCS_CLASS_DECLARE(uct_rc_mlx5_iface_common_t, uct_iface_ops_t*,
uct_rc_iface_ops_t*, uct_md_h, uct_worker_h,
const uct_iface_params_t*, uct_rc_iface_common_config_t*,
uct_rc_mlx5_iface_common_config_t*,
uct_ib_iface_init_attr_t*);
uct_rc_iface_init_attr_t*);


#define UCT_RC_MLX5_TM_STAT(_iface, _op) \
Expand Down
36 changes: 18 additions & 18 deletions src/uct/ib/mlx5/rc/rc_mlx5_iface.c
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Original file line number Diff line number Diff line change
Expand Up @@ -826,7 +826,7 @@ UCS_CLASS_INIT_FUNC(uct_rc_mlx5_iface_common_t, uct_iface_ops_t *tl_ops,
uct_worker_h worker, const uct_iface_params_t *params,
uct_rc_iface_common_config_t *rc_config,
uct_rc_mlx5_iface_common_config_t *mlx5_config,
uct_ib_iface_init_attr_t *init_attr)
uct_rc_iface_init_attr_t *init_attr)
{
uct_ib_mlx5_md_t *md = ucs_derived_of(tl_md, uct_ib_mlx5_md_t);
uct_ib_device_t *dev;
Expand All @@ -844,20 +844,20 @@ UCS_CLASS_INIT_FUNC(uct_rc_mlx5_iface_common_t, uct_iface_ops_t *tl_ops,
return UCS_ERR_INVALID_PARAM;
}

init_attr->flags |= UCT_IB_CQ_IGNORE_OVERRUN;
uct_ib_mlx5_parse_cqe_zipping(md, &mlx5_config->super, init_attr);
init_attr->super.flags |= UCT_IB_CQ_IGNORE_OVERRUN;
uct_ib_mlx5_parse_cqe_zipping(md, &mlx5_config->super, &init_attr->super);

status = uct_rc_mlx5_iface_preinit(self, tl_md, rc_config, mlx5_config,
params, init_attr);
params, &init_attr->super);
if (status != UCS_OK) {
return status;
}

self->rx.srq.type = UCT_IB_MLX5_OBJ_TYPE_LAST;
self->tm.cmd_wq.super.super.type = UCT_IB_MLX5_OBJ_TYPE_LAST;
init_attr->rx_hdr_len = UCT_RC_MLX5_MP_ENABLED(self) ?
init_attr->super.rx_hdr_len = UCT_RC_MLX5_MP_ENABLED(self) ?
0 : sizeof(uct_rc_mlx5_hdr_t);
init_attr->xport_hdr_len = ucs_max(sizeof(uct_rc_hdr_t),
init_attr->super.xport_hdr_len = ucs_max(sizeof(uct_rc_hdr_t),
UCT_IB_RETH_LEN);

UCS_CLASS_CALL_SUPER_INIT(uct_rc_iface_t, tl_ops, ops, tl_md, worker,
Expand Down Expand Up @@ -905,7 +905,7 @@ UCS_CLASS_INIT_FUNC(uct_rc_mlx5_iface_common_t, uct_iface_ops_t *tl_ops,

status = uct_rc_mlx5_iface_init_fence_flags(
self, rc_config, md, dev,
(init_attr->qp_type == IBV_QPT_RC) &&
(init_attr->super.qp_type == IBV_QPT_RC) &&
md->super.relaxed_order_required);
if (status != UCS_OK) {
goto cleanup_dm;
Expand Down Expand Up @@ -996,22 +996,22 @@ UCS_CLASS_INIT_FUNC(uct_rc_mlx5_iface_t,
uct_rc_mlx5_iface_config_t *config = ucs_derived_of(tl_config,
uct_rc_mlx5_iface_config_t);
uct_ib_mlx5_md_t *md = ucs_derived_of(tl_md, uct_ib_mlx5_md_t);
uct_ib_iface_init_attr_t init_attr = {};
uct_rc_iface_init_attr_t init_attr = {};
ucs_status_t status;

init_attr.fc_req_size = sizeof(uct_rc_pending_req_t);
init_attr.flags = IBV_DEVICE_TM_FLAGS(&md->super.dev) ?
UCT_IB_TM_SUPPORTED : 0;
init_attr.cq_len[UCT_IB_DIR_TX] = config->super.tx_cq_len;
init_attr.qp_type = IBV_QPT_RC;
init_attr.max_rd_atomic = IBV_DEV_ATTR(&md->super.dev,
max_qp_rd_atom);
init_attr.tx_moderation = config->super.tx_cq_moderation;
init_attr.dev_name = params->mode.device.dev_name;
init_attr.super.fc_req_size = sizeof(uct_rc_pending_req_t);
init_attr.super.flags =
IBV_DEVICE_TM_FLAGS(&md->super.dev) ? UCT_IB_TM_SUPPORTED : 0;
init_attr.super.cq_len[UCT_IB_DIR_TX] = config->super.tx_cq_len;
init_attr.super.qp_type = IBV_QPT_RC;
init_attr.super.max_rd_atomic = IBV_DEV_ATTR(&md->super.dev,
max_qp_rd_atom);
init_attr.super.tx_moderation = config->super.tx_cq_moderation;
init_attr.super.dev_name = params->mode.device.dev_name;

if ((md->dp_ordering_cap_devx.rc == UCT_IB_MLX5_DP_ORDERING_OOO_ALL) ||
md->ddp_support_dv.rc) {
init_attr.flags |= UCT_IB_DDP_SUPPORTED;
init_attr.super.flags |= UCT_IB_DDP_SUPPORTED;
}

status = uct_rc_mlx5_dp_ordering_ooo_init(md, &self->super,
Expand Down
24 changes: 17 additions & 7 deletions src/uct/ib/rc/base/rc_ep.c
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Original file line number Diff line number Diff line change
Expand Up @@ -118,20 +118,29 @@ void uct_rc_ep_cleanup_qp(uct_rc_ep_t *ep,

ucs_assertv(cq_credits < (UINT16_MAX / 2), "cq_credits=%d", cq_credits);

ucs_list_del(&ep->list);
uct_rc_iface_remove_qp(iface, qp_num);

cleanup_ctx->super.cbq = &iface->super.super.worker->super.progress_q;
cleanup_ctx->super.cb = uct_rc_iface_qp_cleanup_progress;
cleanup_ctx->iface = iface;
cleanup_ctx->qp_num = qp_num;
cleanup_ctx->cq_credits = cq_credits;
ucs_list_add_tail(&iface->qp_gc_list, &cleanup_ctx->list);

status = uct_ib_device_async_event_wait(&md->dev,
IBV_EVENT_QP_LAST_WQE_REACHED,
qp_num, &cleanup_ctx->super);
ucs_assert_always(status == UCS_OK);
/* The LAST_WQE event is generated only for QPs with SRQ, otherwise the
* transport has to trigger the cleanup by itself by calling
* uct_rc_iface_qp_cleanup_progress() directly */
if (!iface->config.srq_disable) {
Comment thread
GuangguanWang marked this conversation as resolved.
cleanup_ctx->super.cbq = &iface->super.super.worker->super.progress_q;
cleanup_ctx->super.cb = uct_rc_iface_qp_cleanup_progress;
status = uct_ib_device_async_event_wait(&md->dev,
IBV_EVENT_QP_LAST_WQE_REACHED,
qp_num, &cleanup_ctx->super);
ucs_assert_always(status == UCS_OK);
} else {
/* Nothing is registered, so mark the waiting context as empty. */
cleanup_ctx->super.cb = NULL;
cleanup_ctx->super.cbq = NULL;
cleanup_ctx->super.cb_id = UCS_CALLBACKQ_ID_NULL;
}
}

UCS_CLASS_INIT_FUNC(uct_rc_ep_t, uct_rc_iface_t *iface, uint32_t qp_num,
Expand Down Expand Up @@ -186,6 +195,7 @@ static UCS_CLASS_CLEANUP_FUNC(uct_rc_ep_t)

ucs_debug("destroy rc ep %p", self);

ucs_list_del(&self->list);
uct_rc_ep_pending_purge(&self->super.super,
uct_rc_ep_pending_purge_warn_cb, self);
uct_rc_fc_cleanup(&self->fc);
Expand Down
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