Currently by default the links are configured as bidirectional.
In some applications only one direction is needed. This would save some resources, especially the BRAMs needed for the second RX FIFO.
The aurora IP supports this mode with the Dataflow-Mode flag.
https://docs.amd.com/r/en-US/pg074-aurora-64b66b/Dataflow-Mode
Implementation would require to pass through a new config flag, change the verilog code to instantiate a send and recv variant and adapt the test example, so it uses only a send or a recv kernel per FPGA.
Currently by default the links are configured as bidirectional.
In some applications only one direction is needed. This would save some resources, especially the BRAMs needed for the second RX FIFO.
The aurora IP supports this mode with the Dataflow-Mode flag.
https://docs.amd.com/r/en-US/pg074-aurora-64b66b/Dataflow-Mode
Implementation would require to pass through a new config flag, change the verilog code to instantiate a send and recv variant and adapt the test example, so it uses only a send or a recv kernel per FPGA.