Prepare qcom-next based on tag 'Linux 7.3-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - #1188
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Select SND_SOC_PCM1681 and SND_SOC_ADAU1977_I2C to build the TI PCM1681 DAC and Analog Devices ADAU1977 ADC drivers needed by the nord soundcard. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Document the PCIe PHY found on the Qualcomm Nord platform. Nord has a 32.0 GT/s capable QMP PCIe PHY that can operate in multiple lane configurations using four PHY segments (A/B/C/D). The active topology is selected by firmware through a TCSR configuration register and may be configured as x16, x8+x8, x8+x4+x4, or x8+x4+x2+x2. The binding describes the register regions, clocks, resets, power domains, regulators, PHY provider interface, clock provider interface, and the qcom,link-mode property used by the driver to discover the active lane configuration programmed by firmware. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-1-ed05c6e09240@oss.qualcomm.com
Add the qcom,nord-pcie compatible string to the Qualcomm PCIe controller binding. The Nord PCIe controller is compatible with the SA8775P PCIe controller implementation and reuses the same binding definition. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-2-ed05c6e09240@oss.qualcomm.com
Add the Nord PCIe controller configuration and the platform-specific settings required for correct operation. Nord requires the NO_SNOOP override and L0s to be disabled. It also requires a clock-gating-control (CGC) workaround to address a PCIe power-domain timing-convergence issue. Set the CORE_CLK_CGC_DIS and AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization. The SLV_ACLK_CGC_DIS bit is already configured by hardware reset. This behavior is documented in the private QCTDD11972446 erratum, which is not publicly available. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-3-ed05c6e09240@oss.qualcomm.com
…on header qphy_setbits(), qphy_clrbits() and qphy_checkbits() were duplicated verbatim across phy-qcom-qmp-pcie.c, phy-qcom-qmp-pcie-msm8996.c, phy-qcom-qmp-ufs.c, phy-qcom-qmp-usb.c, phy-qcom-qmp-usbc.c and phy-qcom-qmp-combo.c. Move them to the shared phy-qcom-qmp-common.h, which all of these drivers already include, and drop the local copies. This also makes the helpers available to phy-qcom-qmp-pcie-multiphy.c without introducing yet another copy. Suggested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-4-ed05c6e09240@oss.qualcomm.com
Reuse the existing port resource arrays for Glymur register regions, power domains, and NOCSR resets instead of maintaining duplicate Glymur-specific lists. Attach each PHY instance's power domains to the device created for that PHY. This ensures that the associated GDSCs are managed with the lifetime of the individual PHY device rather than the parent multiphy platform device. Validate the clock-output-names property before using its count for allocation, and use a generic module description. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-5-ed05c6e09240@oss.qualcomm.com
Add support for the Nord Gen5x16 bifurcated QMP PCIe PHY. Nord has a single PCIe PHY block split into four ports which can be used in multiple lane configurations: x16, x8+x8, x8+x4+x4 and x8+x4+x2+x2. The active topology is selected through the link mode configuration register, and the driver exposes the corresponding PHY instances based on that mode. Unlike Glymur, where the PHY is initialized by firmware, Nord requires Linux to program the PHY registers. Add the PLL, TXRXZ, PCS and PCS lane initialization tables, along with the required power-up, power-down and soft-reset sequencing. Add per-port and grouped PHY configurations for all supported Nord lane modes. Also add support for regular PHY resets in addition to the NOCSR reset. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-v4-6-ed05c6e09240@oss.qualcomm.com
pmic_gpio_populate() seeds pad->input_enabled and pad->output_enabled from the hardware MODE_CTL register, so a pad left in DIGITAL_INPUT or DIGITAL_INPUT_OUTPUT mode by the bootloader starts out with the input buffer enabled. Neither direction callback clears the opposite buffer: .direction_output() only packs PIN_CONFIG_LEVEL, which sets output_enabled, and .direction_input() only packs PIN_CONFIG_INPUT_ENABLE, which sets input_enabled. Requesting either direction on such a pad therefore programs MODE_DIGITAL_INPUT_OUTPUT rather than the requested direction. That silently breaks both directions. After gpiod_direction_input() the pad keeps driving the line, since the output buffer is never disabled. And after gpiod_direction_output() pmic_gpio_get_direction() still reports GPIO_LINE_DIRECTION_IN, because it cannot tell plain input from input+output, which makes gpiolib consider the line an input while the driver is driving it. On a board where several regulator-fixed nodes share one PMIC GPIO the shared GPIO proxy reads that direction back and rejects every consumer after the first: reg-fixed-voltage regulator-wcn-core-vm-1p35: setup of GPIO (default) failed: -1 reg-fixed-voltage regulator-wcn-core-vm-1p35: error -EPERM: can't get GPIO Pack the opposite buffer's PIN_CONFIG_*_ENABLE along with the requested direction so that the resulting MODE_CTL is DIGITAL_INPUT or DIGITAL_OUTPUT, never both. pmic_gpio_config_set() programs the registers once after walking all configs, so this stays a single register write. Pads that are genuinely bidirectional can still be described that way through pinconf, which is the interface that has always been able to express it; the gpiolib direction callbacks now mean what gpiolib says they mean. Fixes: 2634475 ("pinctrl: qcom: spmi-gpio: implement .get_direction()") Assisted-by: LLM Link: https://lore.kernel.org/r/20260922065908.477523-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Nord has four PCIe controllers backed by a single quadfurcated Gen5 QMP PHY with four ports (A/B/C/D) and a common PCIe SMMU. The ports can be ganged into x16, x8+x8, x8+x4+x4 or x8+x4+x2+x2 topologies; the topology in effect is selected by firmware through the TCSR link-config mode register, which the PHY driver reads at probe time. Describe the x8+x4+x2+x2 topology, i.e. all four controllers usable, as that is the configuration the boards ship with. Add the controller and SMMU nodes to nord.dtsi, and the PHY node along with the per-controller clocks, resets, GDSCs, interconnects, OPP tables and TLMM pin states to nord-embedded.dtsi. The four PCIe pipe clocks also become available now, so hook them up as GCC parents in place of the <0> placeholders. The controllers and the PHY are left disabled here and enabled per board. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The Nord Robotics Reference Design board routes all four PCIe links, so enable pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and describe the PERST# and WAKE# lines of each root port. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…rs and PHY The Nord Ride Embedded board routes all four PCIe links, so enable pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and describe the PERST# and WAKE# lines of each root port. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-4-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The Nord Ride Embedded board carries a QCA6797AQ (WCN7850) LGA module on a connectivity adapter card hanging off PCIe2. Two PMIC GPIOs gate the module supplies: PWR_CORE (pmau0102_e GPIO6) enables the DBU_CORE_VL, DBU_CORE_VM and DBU_CORE_VH regulators feeding VDD_CORE_VL/VM/VH, and PWR_CTRL1 (pmau0102_e GPIO8) enables DBU4, which produces the 3.3 V rail. PWR_CTRL2 drives DBU3, which is not populated, so it is left alone. Describe those rails, the WCN7850 PMU that derives the chip supplies from them, and the PCIe endpoint node consuming the PMU outputs. Signed-off-by: Yu Zhang (Yuriy) <yu.zhang@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-5-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The IQ10 Robotics Reference Design carries a Hamilton (WCN7850) module on a board-to-board connector hanging off PCIe2, using two lanes. Unlike the Ride Embedded board, the RRD generates the module supplies itself rather than relying on the module DBUs: three discrete buck converters produce VDD_CORE_VL, VDD_CORE_VM and VDD_CORE_VH (0.95 V, 1.35 V and 1.95 V), all gated by WLAN0_CORE_PWR_EN on pmau0102_e GPIO6, while the 3.3 V and 1.8 V I/O rails are strapped to the always-on peripheral rails. WLAN0_EN on pmau0102_e GPIO10 releases the module itself. Describe those rails, the WCN7850 PMU that derives the chip supplies from them, and the PCIe endpoint node consuming the PMU outputs. Assisted-by: LLM Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260915015632.283642-6-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable CONFIG_PHY_QCOM_QMP_PCIE_MULTIPHY as a module to support the shared PCIe3 PHY used by PCIe3a and PCIe3b on the Qualcomm Glymur SoC. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260825-glymur_linkmode_0826-v10-5-56ab597d77e4@oss.qualcomm.com
Add the compatible for the eDP PHY found on the Qualcomm Nord SoC. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-1-e25c073cf1b6@oss.qualcomm.com
Add the compatible for the DisplayPort controller found on the Qualcomm Nord SoC. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-2-e25c073cf1b6@oss.qualcomm.com
Add the binding for the display subsystem (MDSS) found on the Qualcomm Nord SoC. Nord is MDSS 12.1, DP-only (no DSI), with two independent DP controllers. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-3-e25c073cf1b6@oss.qualcomm.com
Add the DPU catalog entry for the Qualcomm Nord SoC (MDSS 12.1, DPU 1499A). Nord is DP-only with no DSI, and provides 8 DSPP blocks, 2 writeback blocks, 8 interfaces and 2 DP controllers. Extend enum dpu_intf with INTF_9 and INTF_10, which Nord is the first platform to use. Note: register addresses and xin_id values in the catalog are borrowed from sm8750 and precedent platforms and are marked with FIXME(REG_ADDR) and FIXME(XIU_MAP); they need verification against a real Nord register map before production use. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-4-e25c073cf1b6@oss.qualcomm.com
Add the MDSS compatible for the Qualcomm Nord SoC, reusing the 57 MBps register bus bandwidth setting shared with the other recent platforms. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-5-e25c073cf1b6@oss.qualcomm.com
Add the DP controller description and compatible for the Qualcomm Nord SoC, which provides two independent DP controllers, both wide-bus capable. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-6-e25c073cf1b6@oss.qualcomm.com
Nord relocates several DP PHY and QSERDES v8 COM registers relative to existing SoCs. Add Nord-specific defines for the relocated and new-only registers in phy-qcom-qmp-qserdes-dp-com-v8.h and phy-qcom-edp.c so Nord sequences can reference them by name. Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-7-e25c073cf1b6@oss.qualcomm.com
… overrides Nord has a different register layout and power-on sequence that the existing hard-coded paths cannot accommodate. Make com_clk_fwd_cfg optional, add phy_tx_lane_cfg and phy_tx_res_cfg callbacks to phy_ver_ops, and add phy_status_reg and bias1_en_2lane fields to qcom_edp_phy_cfg so each SoC can override the defaults. No functional change for existing SoCs; new fields default to zero/NULL. Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-8-e25c073cf1b6@oss.qualcomm.com
…uration tables Nord requires different AUX channel and VCO divider settings compared to existing SoCs. Add edp_phy_aux_cfg_nord and edp_phy_vco_div_cfg_nord with values sourced from HPG Tables 2-1-a and 2-1-b respectively. Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-9-e25c073cf1b6@oss.qualcomm.com
Nord requires different TX voltage-swing and pre-emphasis levels for both eDP and DP modes. Add four pairs of 4x4 tables covering RBR/HBR and HBR2/HBR3 for each mode, sourced from HPG Tables 2-2, 2-4, 2-6-a and 2-6-b, and wrap them in qcom_edp_swing_pre_emph_cfg descriptors. Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-10-e25c073cf1b6@oss.qualcomm.com
…ne callbacks Nord relocates the QSERDES COM CMN_STATUS and C_READY_STATUS registers so the generic sequences cannot be reused. Add qcom_edp_phy_power_on_nord() which powers down all lanes and polls CMN_STATUS_NORD (0x1d0), and qcom_edp_phy_com_resetsm_cntrl_nord() which triggers the reset SM and polls C_READY_STATUS_NORD (0x1f8). Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-11-e25c073cf1b6@oss.qualcomm.com
Nord requires BIAS_EN_CLKBUFLR_EN to be set to 0x1f to enable the internal bias generator and clock buffer, which differs from the value used on existing SoCs. Add qcom_edp_com_bias_en_clkbuflr_nord() per HPG Table 2-1-d. Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-12-e25c073cf1b6@oss.qualcomm.com
…tion callback Nord requires different SSC register values compared to existing SoCs. Add qcom_edp_com_configure_ssc_nord() which programs SSC_PER1/2 with fixed values and link-rate-dependent SSC_STEP_SIZE1/2 for RBR, HBR, HBR2 and HBR3, per HPG Table 2-9. Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-13-e25c073cf1b6@oss.qualcomm.com
Nord uses a 38.4 MHz CXO reference with a different QSERDES v8 COM register layout and PLL coefficients. Add qcom_edp_com_configure_pll_nord() which programs all QSERDES COM PLL registers with link-rate-dependent values for RBR, HBR, HBR2 and HBR3, per HPG Table 2-1-d. Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-14-e25c073cf1b6@oss.qualcomm.com
…ration callbacks Nord requires different LDO levels, TX lane control offsets and TX resistor calibration codes compared to existing SoCs. Add qcom_edp_ldo_config_nord(), qcom_edp_phy_tx_lane_cfg_nord() and qcom_edp_phy_tx_res_cfg_nord() with values per HPG Table 2-1-d. Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-15-e25c073cf1b6@oss.qualcomm.com
…riptor Add qcom_edp_phy_ops_nord wiring all eight Nord-specific callbacks and nord_edp_phy_cfg collecting the Nord AUX, VCO divider, swing/pre-emphasis tables and ver_ops, with phy_status_reg overridden to DP_PHY_STATUS_NORD (0x0110) and bias1_en_2lane set to 0x03 for correct 2-lane operation. Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911-nord-drv-dt-v1-16-e25c073cf1b6@oss.qualcomm.com
The qcom-ethqos driver is moving towards using "rgmii-id" together with PHY-provided delays. However, existing DTBs use "rgmii" and "rgmii-txid" and must remain supported for backwards compatibility. Warn when either of these legacy PHY modes is used to encourage users to migrate to updated DTBs using "rgmii-id". Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-6-bbe3389d0652@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…owest speed On probe the RGMII link clock is initialised at SPEED_1000, which translates to a 250 MHz source clock even when no PHY link is present, drawing unnecessary power. Initialise at SPEED_10 instead; fix_mac_speed updates the rate once a link is established. Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-7-bbe3389d0652@oss.qualcomm.com/ Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Some SoCs gate the EMAC's path to the System NOC behind dedicated clocks that must be enabled before the DMA can reach memory. Add ethqos_noc_clk_cfg and the corresponding fields in the driver-data and runtime structs so each compatible can declare its own set with per-clock rates. The clocks are acquired during probe and enabled/disabled alongside the existing link clock in ethqos_clks_config(). No functional change for existing compatibles. This will help us when we add support for Shikra. Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-8-bbe3389d0652@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Shikra integrates two Qualcomm ETHQOS controllers based on the Synopsys GMAC IP, similar to previous platforms. Register qcom,shikra-ethqos backed by a new shikra_data descriptor that enables the three NOC clocks required for DMA memory access (axi-noc, pcie-tile-axi-noc, stmmaceth) all at 120 MHz, and the 36-bit DMA address width. As part of the NOC clock voting logic, the qcom-ethqos glue driver takes a second enable reference on the "stmmaceth" clock, which is already enabled by the stmmac core. All three clocks in shikra_noc_clks[] must run at 120 MHz for NOC access, and managing "stmmaceth" through the same clk_bulk path keeps the rate-setting and enable/disable together. Link: https://lore.kernel.org/netdev/20260908-shikra_ethernet-v2-9-bbe3389d0652@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Document the Qualcomm Nord integrated DesignWare XPCS compatible. The XPCS resides in an Ethernet power domain and requires its CSR clock for register access, so require the clock and power-domain resources for this compatible. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-1-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Add the Clause 37 USXGMII configuration and state handling required by XPCS variants which use Clause 37 framing for USXGMII. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-2-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Some XPCS integrations do not expose the standard direct or indirect register layout. Allow the platform driver to use optional register read and write callbacks for both Clause 22 and Clause 45 accesses, while retaining the existing access paths when no callbacks are supplied. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-3-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord exposes the DesignWare XPCS register blocks through separate direct-MMIO windows instead of the standard contiguous MMD/register layout. Add accessors that translate MMD accesses to the Nord windows: MMD 3 (PCS), standard registers: SR_XS at 0x0000 MMD 3 (PCS), vendor registers: VR_XS at 0x2000 MMD 1 (PMA/PMD): SR_PMA at 0x3000 MMD 31 (VEND2), standard regs: SR_MII at 0x4000 MMD 31 (VEND2), vendor registers: VR_MII at 0x5000 Each register uses a 32-bit MMIO stride. The vendor bit is removed from the register index before calculating a vendor-window offset. Select these accessors using the Nord synthetic XPCS ID, allow its smaller direct-MMIO resource, and add the Nord USXGMII Clause 37 compatibility. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-4-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
xpcs_plat_init_clk() acquires the optional CSR clock but does not prepare or enable it. Marking the device runtime-active at that point makes the PM core assume that the hardware is already powered. On Nord, once the XPCS CSR clock was described, the first pm_runtime_resume_and_get() accessed XPCS registers without invoking runtime_resume() to enable the clock. The matching runtime put then invoked runtime_suspend() and attempted to disable a clock which was never enabled, producing an already-disabled clock warning. Initialize the runtime-PM state as suspended instead. The first register access now runs the resume callback and enables the CSR clock, while the subsequent suspend callback performs the matching disable. Check and propagate the state-transition error as part of probe. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-5-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
The DW25GMAC introduced a new DMA architecture called Hyper-DMA (HDMA) for virtualization scalability. This is realized by decoupling physical DMA channels(PDMA) from potentially large number of virtual DMA channels(VDMA). The VDMAs provide software abstraction to driver that map to PDMAs for frame transmission and reception. Since 25GMAC is a derivative of XGMAC, majority of IP is common to both. To add support for the HDMA in 25GMAC, a new instance of dma_ops, dw25gmac400_dma_ops is introduced. To support the current needs, a simple one-to-one mapping of dw25gmac's logical VDMA (channel) to TC to PDMAs is used. Most of the other dma operation functions in existing dwxgamc2_dma.c file are reused whereever applicable. Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core. Link: https://lore.kernel.org/netdev/20260402213629.1996133-2-jitendra.vegiraju@broadcom.com/ Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Integrate dw25gmac support into stmmac hardware interface handling. Added a new entry to the stmmac_hw table in hwif.c. Link: https://lore.kernel.org/netdev/20260402213629.1996133-3-jitendra.vegiraju@broadcom.com/ Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord integrates two ETHQOS controllers based on the Synopsys DesignWare XGMAC IP. Each controller has five clocks, one power domain, and ten SMMU stream mappings. Due to a hardware quirk, PCS link-up depends on the EEE clock being enabled. Add the Nord compatible to the common DWMAC schema exceptions used by Qualcomm ETHQOS platforms. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-6-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Some XGMAC integrations place their MTL queues and DMA channels at different offsets from the standard register layout. Allow platform data to override these addresses while retaining the standard layout by default. This follows the approach used by commit 33719b5 ("net: stmmac: dwmac4: Allow platforms to specify some DMA/MTL offsets"). Qualcomm XGMAC hardware similarly uses differently aligned queue and channel registers. Also allow platforms to override the timestamp register base. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-7-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Select the XPCS instance initialized by stmmac when firmware provides a pcs-handle. Reject interfaces that are not supported by the selected PCS. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-8-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord provides two ETHQOS controllers based on the Synopsys DesignWare XGMAC IP. Add their register layout, wrapper configuration for USXGMII, EEE clock handling required for PCS link-up, and platform-specific SGMII loopback control. Link: ttps://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-9-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord requires DW25GMAC HDMA channels to wait for CSR initialization, mappings for channels not exposed to Linux, and independent VDMA and PDMA traffic-class maps. This patch is tightly coupled with the following ongoing series from Broadcom adding the core driver and hwif integration: https://lore.kernel.org/netdev/20260402213629.1996133-2-jitendra.vegiraju@broadcom.com/ https://lore.kernel.org/netdev/20260402213629.1996133-3-jitendra.vegiraju@broadcom.com/ That series is expected to be revised. Before posting this patch, it must be rebased onto the latest Broadcom revision and retested on Qualcomm Nord hardware. Keep this change downstream until those dependencies are satisfied, then revise and post the remaining Qualcomm-specific delta. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Add the EMAC0 and EMAC1 CNOC APB clock IDs to the SE_GCC clock controller bindings for the Qualcomm Nord SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260824-nords_emac_apb_clk-v1-1-290767386bf5@oss.qualcomm.com
Add the EMAC0 and EMAC1 CNOC APB clocks to the SE_GCC clock controller on the Qualcomm Nord SoC. These branch clocks gate the config NoC APB access to the two EMAC controllers and are required for register access to the Ethernet MACs. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260824-nords_emac_apb_clk-v1-2-290767386bf5@oss.qualcomm.com
…mpatible Add the qcom,nord-dwmac-sgmii-phy compatible to the Qualcomm DWMAC SGMII PHY binding. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> Tested-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260923-nord_ethernet_serdes-v1-1-f8ac1c487882@oss.qualcomm.com
Prepare the SGMII Ethernet PHY driver for PHY modes that require a different SerDes programming sequence. Move the SGMII readiness checks into a helper so additional modes can provide their own status checks, and select the initial interface mode through per-compatible match data rather than hardcoding SGMII during probe. This does not change existing SA8775P behavior. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> Tested-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260923-nord_ethernet_serdes-v1-2-f8ac1c487882@oss.qualcomm.com
Nord uses a QMP v7 SerDes block which is an updated version of the SGMII SerDes PHY IP. The SGMII SerDes PHY supports multiple operating modes by programming different SerDes line rates. The driver currently handles SGMII and 2500BASE-X configurations only. Add support for configuring the SerDes to operate at 10.3125 Gbaud, enabling both USXGMII and 10GBASE-R PHY interface modes. Finally, add a driver compatible for Nord. Select USXGMII as the initial interface mode for Nord. phy_power_on() can run before the consumer calls set_mode(), so this ensures that the first calibration selects the 10.3125 Gbaud programming sequence. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> Tested-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260923-nord_ethernet_serdes-v1-3-f8ac1c487882@oss.qualcomm.com
Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and SerDes blocks, clocks, resets, power domains, SMMU streams and DMA queues. Enable both ports on Nord Ride SX in fixed-link USXGMII 10-Gbps mode for connection to the onboard firmware driven Ethernet switch. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm NHLOS team changes XBL for Nord IOT/Embedded variant, leaving ADSP to be powered up by Linux remoteproc, so that Nord IQ10 Qualcomm Linux (QLI) behavior gets aligned with IQ8/9. Drop early_boot flag from Nord ADSP for that purpose. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260930020745.1940933-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Name SHA Commits
tech/bsp/clk b662153 14
tech/bsp/devfreq 0837ca4 7
tech/bsp/interconnect 81fc6e2 1
tech/bsp/sched 9c2e4b8 3
tech/security/firmware-smc 16b0235 9
tech/bsp/soc-infra c79b7bc 28
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc 8c716bc 1
tech/bus/peripherals c191e3d 10
tech/bus/pci/all 0f23f88 41
tech/bus/usb/dwc 6f24600 8
tech/bus/usb/phy b94824d 38
tech/debug/hwtracing fae0f79 27
tech/pmic/misc e7bb366 12
tech/mem/iommu d196108 10
tech/mm/audio/all 5ba9def 10
tech/mm/camss 73f9fb0 54
tech/mm/drm d42e9c7 68
tech/mm/fastrpc fab5742 4
tech/mm/video bbe1a02 57
tech/mm/gpu e065d5a 1
tech/net/ath 722be84 7
tech/net/bluetooth e352848 8
tech/pm/pmdomain 16a7451 3
tech/pm/power 179ed43 13
tech/pm/thermal 2602b17 9
tech/security/crypto 4c71afd 13
tech/security/ice dc34f45 14
tech/security/optee-next 9babb9a 1
tech/storage/all cb6192d 7
tech/all/dt/qcs6490 fdf8383 21
tech/all/dt/qcs9100 3e3223b 22
tech/all/dt/qcs8300 6a513e3 28
tech/all/dt/qcs615 c3eea9f 13
tech/all/dt/agatti 2ca1b63 2
tech/all/dt/eliza fd76dfc 18
tech/all/dt/hamoa 75cc2f2 39
tech/all/dt/glymur e69025f 30
tech/all/dt/kaanapali b395c11 18
tech/all/dt/pakala 9cdd195 13
tech/all/hawi d594f58 20
tech/all/shikra 5e50e3f 198
tech/all/config 00643d8 86
tech/overlay/dt ae50c51 90
tech/all/workaround ebc9406 14
tech/noup/debug/all 9f1e8ae 37
tech/hwe/unoq a2d85fe 4
early/hwe/nord e1575ac 114
early/hwe/staging/nord 972aee4 119