FROMLIST: PCI: qcom-ep: Add PCIe Endpoint support for Monaco - #1216
Open
ziyuezhang-123 wants to merge 6 commits into
Open
ziyuezhang-123 wants to merge 6 commits into
ziyuezhang-123 wants to merge 6 commits into
Conversation
…6 GT/s PHY The QCS8300 16 GT/s x4 QMP PCIe PHY was previously described using only the qcom,sa8775p-qmp-gen4x4-pcie-phy compatible, since no QCS8300-specific compatible existed for this PHY. This was a mistake, as it left the PHY undocumented as QCS8300 hardware and indistinguishable from SA8775P in the binding. Correct this by documenting a dedicated "qcom,qcs8300-qmp-gen4x4-pcie-phy" compatible, with "qcom,sa8775p-qmp-gen4x4-pcie-phy" listed as its fallback compatible. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260921-monaco_ep-v1-1-63c5282fb0db@oss.qualcomm.com/ Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
The QCS8300 PCIe Endpoint controller is compatible with the SA8775P PCIe Endpoint controller and uses the same programming model. Document the QCS8300 compatible string and its fallback to the SA8775P compatible. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260921-monaco_ep-v1-2-63c5282fb0db@oss.qualcomm.com/
…8300 Monaco supports PCIe Endpoint mode on both PCIe controllers. Reuse the existing SA8775P Endpoint PHY programming for the 16 GT/s x2 PHY and add a new 16 GT/s x4 Endpoint PHY configuration with the required RX tuning parameters. This allows both Monaco PCIe controllers to operate reliably in Endpoint mode. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260921-monaco_ep-v1-3-63c5282fb0db@oss.qualcomm.com/
…bling clocks Some Qualcomm platforms require the interconnect bandwidth constraints to be set before enabling the interconnect clocks, otherwise some clocks get stuck in the off state. Move the icc_set_bw() call before clk_bulk_prepare_enable() so the bandwidth vote is in place first. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260921-monaco_ep-v1-4-63c5282fb0db@oss.qualcomm.com/
…00 first The existing pcie1_phy node only listed qcom,sa8775p-qmp-gen4x4-pcie-phy compatible, since no QCS8300-specific compatible was documented for this PHY at the time. Now that qcom,qcs8300-qmp-gen4x4-pcie-phy is documented, list it first with qcom,sa8775p-qmp-gen4x4-pcie-phy as its fallback, matching the order used by the pcie0_ep and pcie1_ep nodes. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260921-monaco_ep-v1-5-63c5282fb0db@oss.qualcomm.com/
Monaco has two PCIe controllers that can operate in Endpoint mode. Describe the Endpoint nodes for both controllers, including their register regions, clocks, interrupts, interconnects, IOMMU mappings, resets, power domains, and PHY connections etc. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260921-monaco_ep-v1-6-63c5282fb0db@oss.qualcomm.com/
ziyuezhang-123
requested review from
a team,
aiquny,
Ricardo Salveti (ricardosalveti) and
Shiraz Hashim (shashim-quic)
September 30, 2026 02:13
|
Merge Check Failed: No Change Task Found No associated change tasks found for CR 4694550 on any of the following entities: Entities:
CR: 4694550 Please ensure the CR has a change task associated with at least one of the entities for this branch. |
Shiraz Hashim (shashim-quic)
approved these changes
Sep 30, 2026
Test Matrix
|
Contributor
|
ziyuezhang-123 mainline PR is not merged, please get it merged first : |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Add PCIe Endpoint support for Monaco (QCS8300) — dt-bindings, PHY configuration, driver fix, and DTS nodes.
Change 1: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add qcs8300 16 GT/s PHY
Document a dedicated "qcom,qcs8300-qmp-gen4x4-pcie-phy" compatible with "qcom,sa8775p-qmp-gen4x4-pcie-phy" as its fallback.
Change 2: dt-bindings: PCI: qcom-ep: Add QCS8300 compatible
Document the QCS8300 PCIe Endpoint compatible string and its fallback to SA8775P.
Change 3: phy: qcom: qmp-pcie: Add endpoint PHY configuration for QCS8300
Add 16 GT/s x4 Endpoint PHY configuration with required RX tuning parameters for Monaco.
Change 4: PCI: qcom-ep: Set initial interconnect bandwidth before enabling clocks
Move icc_set_bw() before clk_bulk_prepare_enable() to avoid clocks getting stuck in the off state.
Change 5: arm64: qcom: monaco: Fix pcie1_phy compatible to list qcs8300 first
List qcom,qcs8300-qmp-gen4x4-pcie-phy first with sa8775p as fallback.
Change 6: arm64: qcom: monaco: Add PCIe Endpoint nodes
Add pcie0_ep and pcie1_ep nodes for both Monaco PCIe controllers operating in Endpoint mode.
Link: https://lore.kernel.org/all/20260921-monaco_ep-v1-0-63c5282fb0db@oss.qualcomm.com/
CRs-Fixed: 4694550