Prepare qcom-next based on tag 'Linux 7.3-rc5' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - #1221
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Add the Clause 37 USXGMII configuration and state handling required by XPCS variants which use Clause 37 framing for USXGMII. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-2-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Some XPCS integrations do not expose the standard direct or indirect register layout. Allow the platform driver to use optional register read and write callbacks for both Clause 22 and Clause 45 accesses, while retaining the existing access paths when no callbacks are supplied. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-3-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord exposes the DesignWare XPCS register blocks through separate direct-MMIO windows instead of the standard contiguous MMD/register layout. Add accessors that translate MMD accesses to the Nord windows: MMD 3 (PCS), standard registers: SR_XS at 0x0000 MMD 3 (PCS), vendor registers: VR_XS at 0x2000 MMD 1 (PMA/PMD): SR_PMA at 0x3000 MMD 31 (VEND2), standard regs: SR_MII at 0x4000 MMD 31 (VEND2), vendor registers: VR_MII at 0x5000 Each register uses a 32-bit MMIO stride. The vendor bit is removed from the register index before calculating a vendor-window offset. Select these accessors using the Nord synthetic XPCS ID, allow its smaller direct-MMIO resource, and add the Nord USXGMII Clause 37 compatibility. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-4-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
xpcs_plat_init_clk() acquires the optional CSR clock but does not prepare or enable it. Marking the device runtime-active at that point makes the PM core assume that the hardware is already powered. On Nord, once the XPCS CSR clock was described, the first pm_runtime_resume_and_get() accessed XPCS registers without invoking runtime_resume() to enable the clock. The matching runtime put then invoked runtime_suspend() and attempted to disable a clock which was never enabled, producing an already-disabled clock warning. Initialize the runtime-PM state as suspended instead. The first register access now runs the resume callback and enables the CSR clock, while the subsequent suspend callback performs the matching disable. Check and propagate the state-transition error as part of probe. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-5-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
The DW25GMAC introduced a new DMA architecture called Hyper-DMA (HDMA) for virtualization scalability. This is realized by decoupling physical DMA channels(PDMA) from potentially large number of virtual DMA channels(VDMA). The VDMAs provide software abstraction to driver that map to PDMAs for frame transmission and reception. Since 25GMAC is a derivative of XGMAC, majority of IP is common to both. To add support for the HDMA in 25GMAC, a new instance of dma_ops, dw25gmac400_dma_ops is introduced. To support the current needs, a simple one-to-one mapping of dw25gmac's logical VDMA (channel) to TC to PDMAs is used. Most of the other dma operation functions in existing dwxgamc2_dma.c file are reused whereever applicable. Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core. Link: https://lore.kernel.org/netdev/20260402213629.1996133-2-jitendra.vegiraju@broadcom.com/ Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Integrate dw25gmac support into stmmac hardware interface handling. Added a new entry to the stmmac_hw table in hwif.c. Link: https://lore.kernel.org/netdev/20260402213629.1996133-3-jitendra.vegiraju@broadcom.com/ Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord integrates two ETHQOS controllers based on the Synopsys DesignWare XGMAC IP. Each controller has five clocks, one power domain, and ten SMMU stream mappings. Due to a hardware quirk, PCS link-up depends on the EEE clock being enabled. Add the Nord compatible to the common DWMAC schema exceptions used by Qualcomm ETHQOS platforms. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-6-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Some XGMAC integrations place their MTL queues and DMA channels at different offsets from the standard register layout. Allow platform data to override these addresses while retaining the standard layout by default. This follows the approach used by commit 33719b5 ("net: stmmac: dwmac4: Allow platforms to specify some DMA/MTL offsets"). Qualcomm XGMAC hardware similarly uses differently aligned queue and channel registers. Also allow platforms to override the timestamp register base. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-7-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Select the XPCS instance initialized by stmmac when firmware provides a pcs-handle. Reject interfaces that are not supported by the selected PCS. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-8-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord provides two ETHQOS controllers based on the Synopsys DesignWare XGMAC IP. Add their register layout, wrapper configuration for USXGMII, EEE clock handling required for PCS link-up, and platform-specific SGMII loopback control. Link: ttps://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-9-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord requires DW25GMAC HDMA channels to wait for CSR initialization, mappings for channels not exposed to Linux, and independent VDMA and PDMA traffic-class maps. This patch is tightly coupled with the following ongoing series from Broadcom adding the core driver and hwif integration: https://lore.kernel.org/netdev/20260402213629.1996133-2-jitendra.vegiraju@broadcom.com/ https://lore.kernel.org/netdev/20260402213629.1996133-3-jitendra.vegiraju@broadcom.com/ That series is expected to be revised. Before posting this patch, it must be rebased onto the latest Broadcom revision and retested on Qualcomm Nord hardware. Keep this change downstream until those dependencies are satisfied, then revise and post the remaining Qualcomm-specific delta. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
This reverts commit e9a6293. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…k voting" This reverts commit 304b282. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…ock to lowest speed" This reverts commit 8631bb2. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…HY modes" This reverts commit 5421528. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…DLL bypass" This reverts commit 9271be4. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…o_init() to void" This reverts commit f30a66d. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…os compatible" This reverts commit 41c1daf. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Enable the IGC drivers to support the Intel I226 NIC card. Signed-off-by: Venkat Ramana Sugamanchi <vsugaman@qti.qualcomm.com>
USB and PCIe GDSCs must remain enabled during system suspend for USB host mode and PCIe non-D3cold use cases. These GDSCs currently use PWRSTS_RET_ON in the GDSC driver, which prevents the gdsc driver from disabling them in hardware after the first enable. Consequently, they remain enabled indefinitely, even after their consumers become inactive, preventing the GDSCs from being powered off when no longer needed. Instead, use the GenPDs synced_poweroff flag to control whether a GDSC is disabled during suspend. USB and PCIe drivers can leave the flag unset when the GDSC must remain enabled, and set it when the GDSC should be powered off. This allows consumer drivers to have more dynamic control over the GDSC power state based on their current use case. The existing gdsc_gx_gdsc() callback also disables the GDSC based on synced_poweroff flag but it polls for GDSC status during disable if synced poweroff flag is set. But few PCIE GDSCs have a VOTABLE flag and should not be polled for status during disable. Hence introduce a new gdsc_synced_poweroff_disable() callback that disables the GDSC based on GenPD synced_poweroff flag but won't poll for status if GDSC has VOTABLE flag. Change-Id: Ic57554e741a9d04729078fa8647f8e10952d6639 Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Use the gdsc_synced_poweroff_disable() as power_off callback for USB GDSCs on Glymur platform. This allows the GDSCs to be disabled during suspend only when the consumer driver explicitly calls dev_pm_genpd_synced_poweroff() before suspend. Consumer drivers can therefore keep the GDSCs powered on during system suspend by not calling dev_pm_genpd_synced_poweroff() before suspend. Change-Id: Ifbf55774c2f4f83a42437051d724e060144e3221 Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
…B GDSC's" This reverts commit 0f238f2. Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
… callback" This reverts commit 08ecb9a. Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Add the necessary board widgets, kcontrols and DAPM routes for max98091 codec support. Enable required DAI format, sysclk and other required configs. Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
Add the LPASS LPI pinctrl driver for the QCS615 SoC. The driver supports 32 GPIOs in the range 0-31 and provides pin control functionality for the LPASS LPI block. Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
The SDCA class driver is useful on non-ACPI platforms where the topology is supplied statically via sdca_class_ops.populate_function. Drop 'depends on ACPI' from SND_SOC_SDCA and guard the ACPI-parsing implementations in sdca_device.c and sdca_functions.c with IS_ENABLED(CONFIG_ACPI), providing empty stubs when ACPI is off. Link: https://lore.kernel.org/all/20260915165652.914893-2-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
The class PM callbacks pull sdca_class_drv out of drvdata, so the built-in class_sdw_driver owns the drvdata slot. That works for the generic case but blocks codec drivers that want to embed sdca_class_drv in their own private struct, they need drvdata for their codec priv. Split the four callbacks into exported helpers that take a struct sdca_class_drv * directly: sdca_class_system_suspend() sdca_class_system_resume() sdca_class_runtime_suspend() sdca_class_runtime_resume() Codec drivers can now compose these into their own dev_pm_ops without going through drvdata. For the built-in class_sdw_driver, add small dev_pm_ops wrappers that fetch drv from drvdata and wire them into sdca_class_pm_ops (kept static; the built-in slave is the only user). No functional change: the built-in class_sdw_driver keeps the same PM semantics; only the internal plumbing shifts to operate on sdca_class_drv instead of struct device *dev. Link: https://lore.kernel.org/all/20260915165652.914893-3-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Split the internal class_sdw_probe/class_sdw_remove functions into caller-friendly library helpers: sdca_class_probe(sdw, drv) sdca_class_remove(drv) The class_sdw_probe/class_sdw_remove callbacks of the built-in class_sdw_driver are now thin wrappers that allocate a bare sdca_class_drv, stash it in drvdata, and defer to the exported helpers. The exported sdca_class_probe() takes a caller-owned struct sdca_class_drv * so codec-specific SoundWire drivers can embed the class state in their own priv struct, own dev_set_drvdata() themselves, and avoid a second allocation. No functional change for the built-in driver. This lays the groundwork for codec-specific SDCA SoundWire drivers that want to compose the class-side probe with their own quirks; the next patches add the class_ops mechanism on top. Link: https://lore.kernel.org/all/20260915165652.914893-4-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Add struct sdca_class_ops with a populate_function callback that lets codec drivers supply the SDCA topology (entities, clusters, init_table, ...) from static tables in place of sdca_parse_function() on DT/non-DisCo platforms. The callback is a pure data source and performs no bus I/O. Codec drivers embed sdca_class_drv in their own priv and register their populate_function through class_ops passed to sdca_class_probe(). Link: https://lore.kernel.org/all/20260915165652.914893-5-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
…index sdca_asoc_populate_dais() sets each DAI id from the SDCA Function's entity array index. ASoC's default of_xlate_dai_name treats the phandle cell as a positional index into the DAI list, so on a Function with non-DAI entries between dataport entities a sound-dai phandle resolves to the wrong DAI. Register a custom of_xlate_dai_name that walks the entity array and returns the dataport entity whose array index matches the cell value. Link: https://lore.kernel.org/all/20260915165652.914893-6-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
# Conflicts: # MAINTAINERS
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/monaco-evk.dts # arch/arm64/boot/dts/qcom/monaco.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/agatti.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile # drivers/remoteproc/qcom_q6v5_pas.c
# Conflicts: # Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml # drivers/dma/qcom/bam_dma.c # drivers/interconnect/qcom/Kconfig # drivers/soundwire/qcom.c # sound/soc/codecs/lpass-rx-macro.c # sound/soc/qcom/sc8280xp.c
# Conflicts: # arch/arm64/configs/defconfig
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/qcs8300-ride.dts
# Conflicts: # drivers/firmware/qcom/Kconfig
# Conflicts: # arch/arm64/configs/defconfig
# Conflicts: # Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml # Documentation/devicetree/bindings/iommu/arm,smmu.yaml # arch/arm64/configs/defconfig # drivers/hwtracing/coresight/coresight-tnoc.c # drivers/interconnect/qcom/Kconfig
…oc SMMU mappings" This is breaking compilation, reverting until issue is fixed. This reverts commit 3b331b7.
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Salendarsingh Gaud (sgaud-quic)
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Name SHA Commits
tech/bsp/clk 8fbbeee 20
tech/bsp/devfreq 0837ca4 7
tech/bsp/interconnect 81fc6e2 1
tech/bsp/sched 9c2e4b8 3
tech/security/firmware-smc 16b0235 9
tech/bsp/soc-infra 3633b44 39
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc 8c716bc 1
tech/bus/peripherals c191e3d 10
tech/bus/pci/all 0f23f88 41
tech/bus/usb/dwc 6f24600 8
tech/bus/usb/phy b94824d 38
tech/debug/hwtracing fae0f79 27
tech/pmic/misc 032f9a1 18
tech/mem/iommu e1fac89 11
tech/mm/audio/all db2ab98 17
tech/mm/camss 73f9fb0 54
tech/mm/drm 9992711 162
tech/mm/fastrpc fab5742 4
tech/mm/video bbe1a02 57
tech/mm/gpu e065d5a 1
tech/net/ath 722be84 7
tech/net/eth 7151807 19
tech/net/bluetooth e352848 8
tech/pm/pmdomain 16a7451 3
tech/pm/power 3faa52e 14
tech/pm/thermal 2602b17 9
tech/security/crypto 4c71afd 13
tech/security/ice dc34f45 14
tech/security/optee-next 9babb9a 1
tech/storage/all f2a8c9a 9
tech/all/dt/qcs6490 fdf8383 21
tech/all/dt/qcs9100 3e3223b 22
tech/all/dt/qcs8300 6a513e3 28
tech/all/dt/qcs615 4bc8635 14
tech/all/dt/agatti 2ca1b63 2
tech/all/dt/eliza fd76dfc 18
tech/all/dt/hamoa 75cc2f2 39
tech/all/dt/glymur a619ea6 33
tech/all/dt/kaanapali b395c11 18
tech/all/dt/pakala 9cdd195 13
tech/all/hawi 0c23f52 35
tech/all/maili a1cdf4f 5
tech/all/shikra fc6960a 206
tech/all/config 481e59d 88
tech/overlay/dt 2dc104b 98
tech/all/workaround ebc9406 14
tech/noup/debug/all 9f1e8ae 37
tech/hwe/unoq a2d85fe 4
early/hwe/nord 5a150ea 120
early/hwe/staging/nord c660417 121