align sky130 and gf180 with upstream

README.md

@@ -141,39 +141,37 @@ Three threshold-voltage variants of the same 7-track library, on a 1.4um `core7`
 
 **Cell categories:** AND, OR, NAND, NOR, XOR, XNOR, INV, BUF, Tristate, MUX, DFF, Scan DFF, Latch, AOI, OAI, ICG, Delay, Adder, Tie, Filler, Decap, Tap, Antenna
 
-Nothing from ICsprout55 is vendored here: LEF, CDL and Verilog are fetched from the upstream repository archive, and liberty and GDS from the matching [release assets](https://github.com/openecos-projects/icsprout55-pdk/releases). See the [PDK README](lambdapdk/icsprout55/README.md) for the collateral that lambdapdk supplies itself, and for the gaps (no DRC/LVS decks, no SRAM, no I/O yet).
-
 ### Sky130 (130nm)
 
-| Library | Type | Cells | Verilog |
-|---------|------|-------|---------|
-| [sky130hd](lambdapdk/sky130/libs/sky130hd) | High Density | ~430 unique | [verilog](lambdapdk/sky130/libs/sky130hd/verilog) |
-| [sky130hdll](lambdapdk/sky130/libs/sky130hdll) | High Density Low Leakage | ~140 unique | [verilog](lambdapdk/sky130/libs/sky130hdll/verilog) |
-| [sky130io](lambdapdk/sky130/libs/sky130io) | I/O cells | Various | [verilog](lambdapdk/sky130/libs/sky130io/verilog) |
+| Library | Type | Cells | Upstream |
+|---------|------|-------|----------|
+| [sky130hd](lambdapdk/sky130/libs/sky130sc.py) | High Density | ~430 unique | `sky130_fd_sc_hd` |
+| [sky130hdll](lambdapdk/sky130/libs/sky130sc.py) | High Density Low Leakage | ~140 unique | `sky130_fd_sc_hdll` |
+| [sky130io](lambdapdk/sky130/libs/sky130io.py) | I/O cells | Various | `sky130_fd_io` |
 
 **Cell categories:** AND, OR, NAND, NOR, XOR, INV, BUF, MUX, DFF, Latch, AOI, OAI, Delay, Tie, Filler, Decap, Tap, Antenna
 
-**Memory macros ([sky130sram](lambdapdk/sky130/libs/sky130sram)):**
+**Memory macros ([sky130sram](lambdapdk/sky130/libs/sky130sram.py)):**
 
-| Configuration | Verilog |
-|--------------|---------|
-| 1RW1R 32x512 | [verilog](lambdapdk/sky130/libs/sky130sram/sky130_sram_2kbyte_1rw1r_32x512_8/verilog) |
+| Configuration | Upstream |
+|--------------|----------|
+| 1RW1R 32x512 | `sky130_sram_macros` |
 
 ### GF180 (180nm)
 
-| Library | Type | Cells | Verilog |
-|---------|------|-------|---------|
-| [gf180mcu_fd_sc_mcu7t5v0](lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu7t5v0) | 7-track | ~230 | [verilog](lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu7t5v0/verilog) |
-| [gf180mcu_fd_sc_mcu9t5v0](lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu9t5v0) | 9-track | ~230 | [verilog](lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu9t5v0/verilog) |
-| [gf180mcu_fd_io](lambdapdk/gf180/libs/gf180mcu_fd_io) | I/O cells | Various | [verilog](lambdapdk/gf180/libs/gf180mcu_fd_io/verilog) |
+| Library | Type | Upstream |
+|---------|------|----------|
+| [gf180mcu_fd_sc_mcu7t5v0](lambdapdk/gf180/libs/gf180mcu.py) | 7-track standard cells | `gf180mcu_fd_sc_mcu7t5v0` |
+| [gf180mcu_fd_sc_mcu9t5v0](lambdapdk/gf180/libs/gf180mcu.py) | 9-track standard cells | `gf180mcu_fd_sc_mcu9t5v0` |
+| [gf180mcu_fd_io](lambdapdk/gf180/libs/gf180io.py) | I/O cells | `gf180mcu_fd_io` |
 
 **Cell categories:** AND, OR, NAND, NOR, XOR, INV, BUF, MUX, DFF, Latch, AOI, OAI, Tristate, Delay, Tie, Filler, Decap, Tap, Antenna
 
-**Memory macros ([gf180sram](lambdapdk/gf180/libs/gf180mcu_fd_ip_sram)):**
+**Memory macros ([gf180sram](lambdapdk/gf180/libs/gf180sram.py)):**
 
-| Configuration | Verilog |
-|--------------|---------|
-| 64x8 to 512x8 | [verilog](lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/verilog) |
+| Configuration | Upstream |
+|--------------|----------|
+| 64x8 to 512x8 | `gf180mcu_fd_ip_sram` |
 
 ### IHP130 (130nm SiGe)
 

lambdapdk/__init__.py

@@ -335,8 +335,10 @@ def get_libs():
         Sky130Lambdalib_la_iovssa, \
         Sky130Lambdalib_la_iovssio
     from lambdapdk.sky130.libs.sky130sc import Sky130_SCHDLibrary, Sky130_SCHDLLLibrary
-    from lambdapdk.sky130.libs.sky130sram import Sky130_SRAM_32x512, \
-        Sky130Lambdalib_SinglePort, Sky130Lambdalib_SinglePortRegfile
+    from lambdapdk.sky130.libs.sky130sram import Sky130_SRAM_32x256, \
+        Sky130_SRAM_8x1024, Sky130_SRAM_32x512, \
+        Sky130Lambdalib_SinglePort, Sky130Lambdalib_DualPort, \
+        Sky130Lambdalib_SinglePortRegfile
 
     return set([
         ASAP7SC7p5RVT(), ASAP7SC7p5SLVT(), ASAP7SC7p5LVT(),
@@ -417,7 +419,9 @@ def get_libs():
         BumpLibrary(),
         Sky130_IOLibrary(),
         Sky130_SCHDLibrary(), Sky130_SCHDLLLibrary(),
-        Sky130_SRAM_32x512(), Sky130Lambdalib_SinglePort(), Sky130Lambdalib_SinglePortRegfile(),
+        Sky130_SRAM_32x256(), Sky130_SRAM_8x1024(), Sky130_SRAM_32x512(),
+        Sky130Lambdalib_SinglePort(), Sky130Lambdalib_DualPort(),
+        Sky130Lambdalib_SinglePortRegfile(),
         Sky130Lambdalib_la_ioanalog(),
         Sky130Lambdalib_la_iobidir(),
         Sky130Lambdalib_la_ioclamp(),

lambdapdk/asap7/libs/fakeram7.py

@@ -451,8 +451,9 @@ def __init__(self):
 
 class FakeRAM7Lambdalib_SinglePortRegfile(LambalibTechLibrary, _LambdaPath):
     def __init__(self):
-        super().__init__("la_spregfile",
-                         FakeRAM7Lambdalib_SinglePort().techlibs)
+        spram = FakeRAM7Lambdalib_SinglePort()
+
+        super().__init__("la_spregfile", spram.techlibs)
         self.set_name("fakeram7_la_spregfile")
 
         # version
@@ -463,7 +464,12 @@ def __init__(self):
         with self.active_dataroot("lambdapdk"):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spregfile.v")
-                self.add_depfileset(Spram(), "rtl")
+                # This PDK's own la_spram, not lambdalib's generic cell: the
+                # regfile wrapper instantiates la_spram, and depending on the
+                # generic one leaves the substitution to an alias the consumer
+                # may never apply -- giving the behavioural model rather than
+                # the macros.
+                self.add_depfileset(spram, "rtl")
 
 
 if __name__ == "__main__":

lambdapdk/freepdk45/libs/fakeram45.py

@@ -151,8 +151,9 @@ def __init__(self):
 
 class FakeRAM45Lambdalib_SinglePortRegfile(LambalibTechLibrary, _LambdaPath):
     def __init__(self):
-        super().__init__("la_spregfile",
-                         FakeRAM45Lambdalib_SinglePort().techlibs)
+        spram = FakeRAM45Lambdalib_SinglePort()
+
+        super().__init__("la_spregfile", spram.techlibs)
         self.set_name("fakeram45_la_spregfile")
 
         # version
@@ -163,7 +164,12 @@ def __init__(self):
         with self.active_dataroot("lambdapdk"):
             with self.active_fileset("rtl"):
                 self.add_file(lib_path / "lambda" / "la_spregfile.v")
-                self.add_depfileset(Spram(), "rtl")
+                # This PDK's own la_spram, not lambdalib's generic cell: the
+                # regfile wrapper instantiates la_spram, and depending on the
+                # generic one leaves the substitution to an alias the consumer
+                # may never apply -- giving the behavioural model rather than
+                # the macros.
+                self.add_depfileset(spram, "rtl")
 
 
 if __name__ == "__main__":

lambdapdk/gf180/README.md

@@ -1,7 +1,79 @@
-This is a refactored copy of the GLobalFoundries 180 library that is compatible with the Silicon Compiler Collection and industry practices. The golden version which might be updated fron time to time can be found at:
+# GF180MCU PDK
 
-volare enable --pdk gf180mcu 3af133706e554a740cfe60f21e773d9eaa41838c
-gf180mcuA
+The GlobalFoundries 180nm MCU open source PDK, wired into SiliconCompiler.
 
-https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/bba05379e6de0e3f7ab818d9052a2dd80d9f5dea/flow/platforms/gf180
-https://github.com/google/gf180mcu-pdk
+**Cell libraries are fetched, not vendored.** Liberty, LEF, GDS, CDL, SPICE and Verilog for the
+standard cells, the IO and the memories are referenced out of the published build of the
+[open_pdks](https://github.com/RTimothyEdwards/open_pdks) revision pinned as `pdk_rev` in
+`_GF180Data` ([`__init__.py`](__init__.py)).
+
+The PDK and every library report that revision's date, `2026-08-27`, as their package version
+(`PDK_VERSION` on the dataroot mixin) — so a manifest says which pin a run used.
+
+| Dataroot | Provides |
+|---|---|
+| `gf180mcu_fd_sc_mcu7t5v0` | 7-track standard cells |
+| `gf180mcu_fd_sc_mcu9t5v0` | 9-track standard cells |
+| `gf180mcu_fd_io` | IO cells |
+| `gf180mcu_fd_ip_sram` | SRAM macros |
+| `common` | the shared `libs.tech` tree — KLayout setup and DRC, Xyce models, some OpenRCX decks |
+| `gf180mcu_fd_sc_mcu7t5v0_tech` | 7-track tech LEFs, all 12 stackups |
+| `gf180mcu_fd_sc_mcu9t5v0_tech` | 9-track tech LEFs, all 12 stackups |
+
+## Variants
+
+open_pdks builds **four** install variants, one per metal stack:
+
+| variant | stackup |
+|---|---|
+| `gf180mcuA` | `3LM_1TM_30K` |
+| `gf180mcuB` | `4LM_1TM_11K` |
+| `gf180mcuC` | `5LM_1TM_9K` |
+| `gf180mcuD` | `5LM_1TM_11K` |
+
+This PDK exposes **eleven** stackups (3/4/5/6LM × 6K/9K/11K/30K) across 22 classes, so seven of them
+have no upstream counterpart. The tech LEFs come from the gf180mcu-pdk repository, which ships every
+stackup whether or not open_pdks installs it.
+
+Only the GDS depends on the variant. The cell LEF, the liberty, the CDL and the SPICE netlist are
+byte-identical across all four, and the SRAM macros are identical in every view — all 76 files — so
+`library_path()` picks a variant from the metal count and everything else follows it.
+
+## What this repository still holds
+
+| Path | What |
+|---|---|
+| `base/apr/` | the two 6LM DEF→GDS layer maps — upstream's stops at Metal5 |
+| `base/pex/openroad/` | 27 OpenRCX decks, for the nine stackups open_pdks does not publish |
+| `base/setup/magic/`, `base/setup/netgen/` | DRC and LVS decks — **not refreshed**, see below |
+| `libs/*/apr/openroad/` | `pdngen_*.tcl`, `global_connect.tcl`, `tapcell.tcl` |
+| `libs/*/techmap/yosys/` | adder, latch and tristate techmaps |
+| `libs/gf180mcu_fd_io/blackbox/` | generated from the LEFs by `scripts/make_blackbox.py` |
+| `libs/*/lambda/` | generated lambdalib views |
+
+## Known gaps
+
+- **The magic and netgen decks are the vendored copies.** Upstream ships `gf180mcuA.tech`,
+  `gf180mcuA.magicrc` and `gf180mcuA_setup.tcl`, but SiliconCompiler pins magic at `c7f11d2`
+  (8.3.367, 2023-02-16) while magic HEAD is 8.3.683. The same block applies as for sky130 — see
+  `lambdapdk/sky130/PATCHES.md`.
+- **Two of the eleven stackups take their OpenRCX decks from upstream.** open_pdks publishes
+  extraction rules for `gf180mcuC` (`5LM_1TM_9K`) and `gf180mcuD` (`5LM_1TM_11K`) only; the other
+  nine keep the vendored decks. The suffix-less upstream form is the matching lineage — `gf180mcuD`'s
+  is byte-identical to the copy this repository carried, where the `.magic` form differs throughout.
+- **6LM keeps its own DEF→GDS layer map.** Upstream's single `klayout/tech/gf180mcu.map` covers
+  Metal1–5 with the same layer numbers, and adds the `Metal<n> PIN` datatype-10 entries the vendored
+  file routed through separate `NAME` lines — but it has no `MetalTop`, which is the only name 6LM
+  gives its top layer. `5LM_1TM_9K` uses the upstream map.
+- **The KLayout DRC runs from upstream's single deck.** It selects rule decks by tag, so the three
+  vendored entry points and their boolean `feol`/`beol` switches collapse into `decks=all|feol|beol|
+  antenna|density` against one runset, with `metal_top` / `metal_level` / `mim_option` passed as
+  before.
+- **Three liberty corners** are registered per library. Upstream ships 15 for the standard cells and
+  12 for the IO in the same dataroot; adding more costs no extra download.
+- **The archives are not subsetted.** SiliconCompiler unpacks each one whole, including the `mag`
+  hierarchy no flow here reads and all four install variants.
+
+## Licensing
+
+Apache 2.0, as upstream.