Senior digital design engineer at lowRISC, postdoctoral researcher at IIS, ETH Zurich. My 2025 Ph.D. was on energy-efficient, real-time data movement for heterogeneous mixed-criticality systems.
I design energy-efficient architectures: memory interconnects, data movement, hardware security, and the ASICs that carry them. So far that adds up to more than 15 tapeouts. I bring chips up on ATE and standalone setups, which is what DUTCTL is for. Most of what I build is open-source silicon, all the way down: software, RTL, EDA tools, PDKs. Basilisk is one example. I also make top-metal chip art and high-fidelity GDSII renders with ArtistIC.
Advising students on their theses is the part I enjoy most. Almost 50 of them so far.
