hardware-description

PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Haskell library for hardware description

A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding

A Framework for System Modeling, Simulation, and Emulation

Provides a Hardware Description of basics arithmetics on posit format.

This repository is being used to store the work for my direct RTL neuron implementation that I am creating as part of my research project.

Hardware Description (and Simulation) Library

DIG-SYSTEM: A high-performance VHDL DPLL for Xilinx FPGAs. Implements IDELAYE2 primitives with sigma-delta dithering for sub-tap resolution. Features adaptive damping, phase velocity tracking, and robust hysteresis locking. Optimized for precision clock and data alignment.

32-bit Single-Cycle RISC-V (RV32I) CPU built completely from scratch using basic logic primitives and universal NAND gates in Logisim-Evolution. Features full datapath, ALU, Control Unit, 32-register file, Data Memory, and support for R-type, I-type, S-type, and B-type instructions.

🚀 Design and simulate digital circuits with VHDL using p5.js for interactive visualizations and educational insights.

🚀 Explore VHDL designs for Year 7 projects, enhancing learning in digital logic through hands-on examples and simulations.