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Cannot get verbose commit log output from Dromajo+BOOM cosimulation #2332

Description

@Lruos

Background Work

Feature Description

I am trying to enable Dromajo co-simulation with a BOOM core in Chipyard, and I want to print the detailed commit log (similar to Spike: … vs Cosim: … lines shown in some existing logs). However, I cannot get that verbose output.

What I did:

Added the three required config fragments (WithTraceIO, WithTraceIOPunchthrough, WithSimDromajoBridge) to my BOOM config (or used DromajoBoomConfig).

Built with ENABLE_DROMAJO=1.

Modified dromajo_cosim.cpp and changed verbose = true.

Rebuilt Dromajo and reran simulation.

Also tried running with make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY=<my_bin> run-binary.

Motivating Example

Expected behavior:
The simulation should print line‑by‑line commit logs into uartlog like the example below (found from another user):

text
Spike: core 0: 3 0x0000000080002004 (0x0000fdb7) lui s11,0xf x27 0x000000000000f000
DUT: Cosim: 1583 commit: 80002004 (0xfdb7) lui s11, 0xf x27 0xf000(DUT)
Observed behavior:

The simulation runs but only prints Dromajo error‑type messages (or prints nothing at all to uartlog).

Or, the simulation does not print any line‑by‑line commit information.

My environment:

Chipyard commit hash: (please provide)

Chipyard version/tag: (e.g., 1.12.0, 1.13.0, etc.)

BOOM config used: (e.g., DromajoBoomConfig, MyDromajoBoomConfig, LargeBoomConfig with mixins)

Simulator: (Verilator / VCS / FireSim)

Attempts to debug:

Verified Dromajo is compiled with verbose=true.

Confirmed ENABLE_DROMAJO is set and the design includes the Dromajo bridge.

Tried both VCS and Verilator simulations.

Searched existing issues (and found none showing the same problem).

Question:
What are the exact steps required to enable the detailed, line‑by‑line commit log (Spike vs DUT) for a BOOM + Dromajo cosimulation in Chipyard? Are there any additional steps or configuration options I am missing?

Thank you!

Activity

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