Shared PTW and other VM improvements - #392

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ATWeatherly wants to merge 14 commits into

vortexgpgpu:masterfrom

ATWeatherly:shared-ptw-pr

Commits on Aug 27, 2026

simx: gate the cache flush walk on pipe occupancy, not TFifo::empty()

ATWeatherly
and
claude
committed
60245f6
simx: group arbiter inputs by CDIV like VX_stream_arb

ATWeatherly
and
claude
committed
e5c812a
vm: fix RTL VM build under PERF_ENABLE, satp width, TLB sizing, dead BARE cases

authored and
ATWeatherly
committed
eb615f9
vm: shared multi-walker page-table walker with walk caches; banked TLBs; Sv39

authored and
ATWeatherly
committed
7c9b744
vm: SimX timing model for the shared walker, banked TLBs, walk caches

authored and
ATWeatherly
committed
512ffe6
vm: rtlsim and xrt CI coverage, vm_stress test, docs; fix VX_MEM_PHYS VA overlap

authored and
ATWeatherly
committed
255e996
cp: RTL command-processor VM (CP_SATP, DEV_CAPS.VM_ENABLED, DMA walker)

authored and
ATWeatherly
committed
f7c42f6
mmu: size the bypass-path full address by VX_CFG_MEM_ADDR_WIDTH

ATWeatherly
and
claude
committed
5c92062
simx: keep a TLB-missing access in its ReqIn port until it is replayed

ATWeatherly
and
claude
committed
1b92dd0
unittest: connect the new CP satp port in the regfile and DMA testbenches

ATWeatherly
and
claude
committed
824ba39
simx: model the banked-TLB lookup pipeline; add VM model_parity cases

ATWeatherly
and
claude
committed
f405e31
cp: fix the DMA walker's Sv32 root slice, invalidate its translation cache, share VM geometry

ATWeatherly
and
claude
committed
9aa288d
mmu: drop fills from walks that straddle a flush (RTL and SimX)

ATWeatherly
and
claude
committed
bfaae66
simx,runtime: PTW sizing by instantiated cores, VM hygiene

ATWeatherly
and
claude
committed
54381bb

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Shared PTW and other VM improvements - #392

Shared PTW and other VM improvements#392
ATWeatherly wants to merge 14 commits into
vortexgpgpu:masterfrom
ATWeatherly:shared-ptw-pr

Commits on Aug 27, 2026

simx: gate the cache flush walk on pipe occupancy, not TFifo::empty()

simx: group arbiter inputs by CDIV like VX_stream_arb

vm: fix RTL VM build under PERF_ENABLE, satp width, TLB sizing, dead BARE cases

vm: shared multi-walker page-table walker with walk caches; banked TLBs; Sv39

vm: SimX timing model for the shared walker, banked TLBs, walk caches

vm: rtlsim and xrt CI coverage, vm_stress test, docs; fix VX_MEM_PHYS VA overlap

cp: RTL command-processor VM (CP_SATP, DEV_CAPS.VM_ENABLED, DMA walker)

mmu: size the bypass-path full address by VX_CFG_MEM_ADDR_WIDTH

simx: keep a TLB-missing access in its ReqIn port until it is replayed

unittest: connect the new CP satp port in the regfile and DMA testbenches

simx: model the banked-TLB lookup pipeline; add VM model_parity cases

cp: fix the DMA walker's Sv32 root slice, invalidate its translation cache, share VM geometry

mmu: drop fills from walks that straddle a flush (RTL and SimX)

simx,runtime: PTW sizing by instantiated cores, VM hygiene